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This Verilog FAQ is a bit old copy of the Verilog FAQ found in the net. I have added some questions to it based on the ones that I get frequently from my website readers. I tried many times to write Verilog FAQs, but could not complete it as I was trying to do too many things at the same time. If you find anything to be added/deleted to this FAQ, please don't hesitate to write to me.

   

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I have divided Verilog FAQ into General, Technical, Tools and Misc sections. I may add more sections according to the user feedback.

   

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  General
   
Introduction
What is the difference between Verilog and VHDL ?
Whose bright idea was this?
What is comp.lang.verilog?
Is there an archive for this group?
Is the archive available on the Web?
What is PLI?
Is there a free verilog parser available?
Is there a free Verilog simulator?
Where can I find a free Verilog quick reference card?
Are there related Web sites?
I want to learn Verilog, how do I start?
Are there good technical papers on Verilog and design problems ?
Is there any web resource for questions asked in interview ?
Is there any web resource for checking my Verilog skills ?
   

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  Technical
   
How do I generate clock in Verilog ?
How do I test my design xyz ?
What is the difference between wire and reg ?
What is the difference between blocking and nonblocking assignment ?
How do I write a state machine in Verilog ?
How do I avoid Latch in Verilog ?
How does this xyz code get synthesized ?
How do I implement Memories in Verilog ?
How do I read and write from a file ?
What is this `timescale compiler directive ?
Can we mix blocking and nonblocking in one always block ?
   

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  Tools
   
Where can I get a free version of a Verilog Simulator ?
Is there any student version of commercial simulators ?
What is VCD and is there any free tool to view it ?
Which is the best Verilog simulator ?
What is the difference between cycle and event based Verilog simulators ?
What is the difference between compiled and interpreted Verilog simulator ?
Where can I get a student version of a Synthesis tool ?
Is there any text editor with Verilog syntax highlighting ?
   

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  Miscellaneous
   
I am fresh from college; how can I get into ASIC/VLSI domain?
I am doing my final semester and I want some good project in Verilog.
Where can I find code for I8155 and xyz code ? (Well I was given this assignment at my college)
I want to learn Verilog, and ASIC design. Is there any good training institute around ?
Which are the companies that use Verilog for designing Chips ? (Well I want to apply for a job to these companies)
   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com