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		I been getting mails from engineers asking if I can forward their resume to someone I know. I thought may be I can put some requirements that I had come across in big companies here in last few days. In any case you are always welcome to drop your resume to me at deepak@asic-world.com

		Companies which want to see their requirements posted, just drop me a mail. I will post your requirement here free of charge.

		Following requirements are for SmartDV Technologies for their operations in Bangalore, India. You can visit them at www.smart-dv.com

		POSITION : Verification Engineer
		- 7+ Years of experience in ASIC verification
		- Should have tapped out atleast 2 chips from specs to post silicon debug
		- Should have experience in creating testbenches from scratch
		- Should have very good understanding of coverage driven verification closure
		- Strong knowledge of Verilog, HVL (VERA or SystemVerilog or e (Specman))
		- Very good experience in writing scripts in Perl or Python or TCL
		- Independent team player with excellent communication skills
		- Knowledge of C++




		Engineer Trainee
		- B.E or MTech from reputed university with 0-2 years experience.
		- Strong understanding of Digital design
		- Working experience with Verilog or VHDL or SystemVerilog
		- Experience in writing C or C++ code
		- Understanding of OOPS.
		- Knowledge of Perl or Python or TCL scripting languages
		- Very good academic track record
		- Even Freshers can apply.

Do you have any Comment? mail me at:deepak@asic-world.com