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Simulation-related constructs
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This section covers the simulation related constructs that can be used withing e language, some of them are as given below.
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- 'HDL pathname'
- force
- release
- simulator_command()
- stop_run()
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'HDL pathname'
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This is used for accessing a HDL node inside the design. We can use this for either driving a value or for releasing a value.
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Parameter
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Description
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HDL-pathname
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The full path name of an HDL object, optionally including expressions and composite data.
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bit-range
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A bit range has the format [high-bit-num
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index-exp
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Accesses a single bit of a Verilog vector, a single element of a Verilog memory, or a single vector of a VHDL array of vectors.
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@x | z
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Sets or gets the x or z component of the value. When this notation is not used in accessing an HDL object, x is translated to zero and z to one. When reading HDL objects using @x (or @z), we get value (x or z) to one, and all other values to zero. When writing HDL objects, if @x (or @z) is specified, every bit that has a value of one to x (or z). In this way, @x or @z acts much like a data mask, manipulating only those bits that match the value of x or z.
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@n
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When this specifier is used for driving HDL objects, the new value is visible immediately (now). The default mode is to buffer projected values and update only at the end of the tick. If reading a value using @n then the projected simulator value can be seen.
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force
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This forces an HDL object to a specified value, overriding the current value and preventing the DUT from driving any value. The HDL object remains at the specified value until a subsequent force action from e or until freed by a release action.
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release
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This releases the HDL object which previously has been forced.
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simulator_command()
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This passes a command to the HDL simulator from e. The command shall not return a value. The output of the command is sent to the standard output and log file.
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This routine can be used only with the ModelSim, SpeedSim, and NC (VHDL) simulators.
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stop_run()
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This stops the simulator and initiates post-simulation phases. This method needs to be called by a user defined method or TCM to stop the simulation run cleanly. The following things occur when stop_run() is invoked.
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- The quit() method of each struct under sys is called. Each quit() method emits a quit event for that struct instance at the end of the current tick.
- All executing threads shall continue until the end of the current tick.
- At the end of the current tick, the extract, check, and finalize test phases are performed.
- If a simulator is linked here, e terminates the simulation cleanly after the test is finalized.
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Verilog Statements
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Some basic functionality of the Verilog simulator interface, such as setting or sampling the values of some Verilog objects, is enabled without any action on your part. However, some features, such as the continuous driving of Verilog signals or calling of Verilog tasks and functions, requires some user-specified declarations-- verilog statements or unit members. The following sections describe these constructs
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- verilog code
- verilog function
- verilog import
- verilog task
- verilog time
- verilog variable reg | wire
- verilog variable memory
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Verilog Code
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Specifies a list of Verilog strings to be included in the Verilog stubs file each time it is generated. The stubs file contains code that enables some Verilog-related features.
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Verilog Function
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Declares a Verilog function in e so that it can be called from a time-consuming method (TCM).
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Verilog Task
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Declares a Verilog user-defined task or system task in e so that it can be called from a TCM.
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Verilog Import
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Reads in a file that includes Verilog `define text macros. After reading in the file, you can use these text macros in e code.
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Verilog Time
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Sets the time resolution in the Verilog stubs file to the specified verilog-time-scale.
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Verilog variable reg | wire
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Allows access in e code to the Verilog object named in 'HDL-pathname', a register or a net. In general, you can access Verilog objects using the 'HDL-pathname' expression. The verilog variable statement is necessary only when you want to
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- drive or force a wire
- drive or sample a wire or reg with an offset from the e callback
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Verilog variable memory
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Allows access in e to a Verilog memory. verilog variable declarations for the same memory can be repeated (to allow incremental building of e code), but each repeated declaration must be identical.
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