Verification Links




		HVL Compilers Specman : This compiler/debugger/simulator is for e language, the most popular of all the HVL's Vera : This compiler/simulator is for VERA language, lately lot of good features have been added both to compiler and also VERA language. TestBuilder : This is set of free C++ class packeges for writing HCL testbenches. I love this tool. SystemC SCV : Testbuilder team added verification capability to systemC. I personally feel this is better then Testbuilder.

		Design Verification Services Smart Design Verification : This company develops SystemVerilog Verification IP for GigaBit Ethernet, 10G Ethernet, LIN Protocol, CAN, I2C, AMBA. Also provides design and verification services. Wipro : This company provides complete ASIC design and verification soultions. HCL : This company provides complete ASIC design and verification soultions.

		Verilog Simulators Verilog-XL : This is the most standard simulator in the market, as this is the sign off simulator. NCVerilog : This is the compiled simulator which works as fast as VCS, and still maintains the sign off capabilities of Verilog-XL. This simulator is good when it comes to gate level simulations. VCS : This is worlds fastest simulator, this is also a compiled simulator like NCverilog. This simulator is faster when it comes to RTL simulation. Few more things about this simulator are direct C kernel interface, Covermeter code coverage embedded, better integration with VERA and other Synopsys tools. Finsim : This is 100% compatible simulator with Verilog-XL, runs on Linux, Windows and Solaris. This is compiled simulator like VCS and NCVerilog, but slower then VCS and NCVerilog. A $100 version is available, but I wonder what good this can do to Students ? Modelsim : This is most popular simulator, It has got very good debugger, it supports SystemC, Verilog, VHDL and SystemVerilog.

		Free Simulators Icarus Verilog : This is best Free Verilog simulator out there, it is simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. Icarus continues to get better and better. Icarus is being used for real design work by companies now as a simulator, and is starting to be useful as a synthesizer for a Xilinx FPGA flow as well. All my tutorials are compiled on this compiler.

		VCD Viewer nWave : One of the best VCD viewer, with support for large VCD dumps. Undertow : Undertow waveform viewer. GTKWave : Freeware VCD viewer, Seems far better then other free VCD viewers. Dinotrace : Freeware VCD viewer from veritools

		Code Coverage Verification Navigator : An integrated design verification environment that enables a consistent, easy-to-use and efficient verification methodology with a powerful set of best-in-class tools for managing the HDL verification process. These tools include HDL checking, coverage analysis, test suite analysis and FSM analysis. The environment includes an extensible flow manager for easy incorporation of custom verification flows. Verification Navigator supports Verilog, VHDL and mixed language designs and integrates seamlessly with all leading simulation environments. SureCov : Engineering teams designing today's chips and semiconductor IP cores need to know, with confidence, how thoroughly the functional test suite is exercising the design. Verisity's SureCov measures FSM and code coverage with the lowest simulation overhead of any tool available, and without requiring changes to the source design. The SureSight graphical user interface shows exactly which parts of the design have been covered and which have not. Code Coverage Tool : A freeware code coverage tool. Code coverage tool is a Verilog code coverage analysis tool that can be useful for determining how well a test suite is covering the design under test.

		Linting Leda : Leda is a code purification tool for designers using the Verilog® and VHDL Hardware Description Language (HDL). Leda is uniquely qualified to analyze HDL code pre-synthesis and pre-simulation and is totally compatible with all popular synthesis and simulation tools and flows. By automating more than 500 design checks for language syntax, semantics and questionable synthesis/simulation constructs, Leda detects common as well as subtle and hard-to-find code defects, thus freeing designers to focus on the art of design. HDLint : A power full linting tool for VHDL and Verilog. nLint : nLint is a comprehensive HDL design rule checker fully integrated with the Debussy debugging system. SureLint : Designers need tools to analyze and debug their designs before integrating with the rest of the project. SureLint offers finite state machine (FSM) analysis, race detection, and many additional checks the most complete lint tool on the market.

		Utils FSMDesigner : FSMDesigner is a Java-based Finite State Machine (FSM) editor, which allows the hardware designer to specify complex control circuits in an easy and comfortable way. The graphical FSM is converted into a proprietary state/flow-table format called fsm2. It can be translated into efficient and synthesizable Verilog HDL code by a compiler called fsm2v designed at our chair. FSMDesigner is based on the Simple-Moore FSM model, which completely eliminates the output function by using parts of the state vector as outputs. TimeGen : TimeGen is an engineering CAD tool which allows a digital design engineer the capability to quickly and effectively draw digital timing diagrams. The waveforms can easily be exported to other Window programs, such as Microsoft Word, for use in writing design specifications. TimeGen is less price compared to other tools. Waveformer : Tool for drawing waveforms, to be used for documentation purpose. Timing Tool : TimingTool is a free to use on-line Timing Diagram Editor. This tool provides very good VHDL and Verilog test benches and requires no download or installation. Perlilog : Perlilog is a design tool, whose main target is easy integration of Verilog IP cores for System-on-Chip (SoC) designs. The philosophy behind Perilog is that an IP core should be like a black box. Fitting it for a certain purpose should be as easy as defining the desired requirements. Connecting the cores, to become a system, should be as easy as drawing a block diagram. Perlilog is written in Perl, currently with no GUI. While the scripts, that the system consists of, are rather sophisticated, only plain Perl knowledge is needed to use its scripting capabilities.

Do you have any Comment? mail me at:deepak@asic-world.com