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Introduction
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Verilog has built in primitives like gates, transmission gates, and switches. These are rarely used in design (RTL Coding), but are used in post synthesis world for modeling the ASIC/FPGA cells; these cells are then used for gate level simulation, or what is called as SDF simulation. Also the output netlist format from the synthesis tool, which is imported into the place and route tool, is also in Verilog gate level primitives. |
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Note : RTL engineers still may use gate level primitivies or ASIC library cells in RTL when using IO CELLS, Cross domain synch cells. |
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Gate Primitives
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The gates have one scalar output and multiple scalar inputs. The 1st terminal in the list of gate terminals is an output and the other terminals are inputs. |
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Gate
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Description
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and
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N-input AND gate
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nand
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N-input NAND gate
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or
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N-input OR gate
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nor
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N-input NOR gate
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xor
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N-input XOR gate
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xnor
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N-input XNOR gate
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Examples
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1 module gates();
2
3 wire out0;
4 wire out1;
5 wire out2;
6 reg in1,in2,in3,in4;
7
8 not U1(out0,in1);
9 and U2(out1,in1,in2,in3,in4);
10 xor U3(out2,in1,in2,in3);
11
12 initial begin
13 $monitor(
14 "in1=%b in2=%b in3=%b in4=%b out0=%b out1=%b out2=%b",
15 in1,in2,in3,in4,out0,out1,out2);
16 in1 = 0;
17 in2 = 0;
18 in3 = 0;
19 in4 = 0;
20 #1 in1 = 1;
21 #1 in2 = 1;
22 #1 in3 = 1;
23 #1 in4 = 1;
24 #1 $finish;
25 end
26
27 endmodule
You could download file gates.v here
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in1 = 0 in2 = 0 in3 = 0 in4 = 0 out0 = 1 out1 = 0 out2 = 0
in1 = 1 in2 = 0 in3 = 0 in4 = 0 out0 = 0 out1 = 0 out2 = 1
in1 = 1 in2 = 1 in3 = 0 in4 = 0 out0 = 0 out1 = 0 out2 = 0
in1 = 1 in2 = 1 in3 = 1 in4 = 0 out0 = 0 out1 = 0 out2 = 1
in1 = 1 in2 = 1 in3 = 1 in4 = 1 out0 = 0 out1 = 1 out2 = 1
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Transmission Gate Primitives
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Transmission gates are bi-directional and can be resistive or non-resistive. |
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Syntax: keyword unique_name (inout1, inout2, control); |
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Gate
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Description
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not
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N-output inverter
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buf
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N-output buffer.
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bufif0
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Tri-state buffer, Active low en.
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bufif1
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Tri-state buffer, Active high en.
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notif0
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Tristate inverter, Low en.
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notif1
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Tristate inverter, High en.
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Transmission gates tran and rtran are permanently on and do not have a control line. Tran can be used to interface two wires with seperate drives, and rtran can be used to weaken signals. |
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Examples
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1 module transmission_gates();
2
3 reg data_enable_low, in;
4 wire data_bus, out1, out2;
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6 bufif0 U1(data_bus,in, data_enable_low);
7 buf U2(out1,in);
8 not U3(out2,in);
9
10 initial begin
11 $monitor(
12 "@%g in=%b data_enable_low=%b out1=%b out2= b data_bus=%b",
13 $time, in, data_enable_low, out1, out2, data_bus);
14 data_enable_low = 0;
15 in = 0;
16 #4 data_enable_low = 1;
17 #8 $finish;
18 end
19
20 always #2 in = ~in;
21
22 endmodule
You could download file transmission_gates.v here
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@0 in = 0 data_enable_low = 0 out1 = 0 out2 = 1 data_bus = 0
@2 in = 1 data_enable_low = 0 out1 = 1 out2 = 0 data_bus = 1
@4 in = 0 data_enable_low = 1 out1 = 0 out2 = 1 data_bus = z
@6 in = 1 data_enable_low = 1 out1 = 1 out2 = 0 data_bus = z
@8 in = 0 data_enable_low = 1 out1 = 0 out2 = 1 data_bus = z
@10 in = 1 data_enable_low = 1 out1 = 1 out2 = 0 data_bus = z
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Switch Primitives
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There are six different switch primitives (transistor models) used in Verilog, nmos, pmos and cmos and the corresponding three resistive versions rnmos, rpmos and rcmos. The cmos type of switches have two gates and so have two control signals. |
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Syntax: keyword unique_name (drain. source, gate) |
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Gate
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Description
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1. pmos
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Uni-directional PMOS switch
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1. rpmos
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Resistive PMOS switch
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2. nmos
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Uni-directional NMOS switch
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2. rnmos
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Resistive NMOS switch
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3. cmos
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Uni-directional CMOS switch
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3. rcmos
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Resistive CMOS switch
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4. tranif1
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Bi-directional transistor (High)
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4. tranif0
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Bi-directional transistor (Low)
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5. rtranif1
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Resistive Transistor (High)
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5. rtranif0
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Resistive Transistor (Low)
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6. tran
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Bi-directional pass transistor
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6. rtran
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Resistive pass transistor
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7. pullup
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Pull up resistor
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8. pulldown
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Pull down resistor
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Transmission gates are bi-directional and can be resistive or non-resistive. Resistive devices reduce the signal strength which appears on the output by one level. All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high impedance outputs. |
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Examples
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1 module switch_primitives();
2
3 wire net1, net2, net3;
4 wire net4, net5, net6;
5
6 tranif0 my_gate1 (net1, net2, net3);
7 rtranif1 my_gate2 (net4, net5, net6);
8
9 endmodule
You could download file switch_primitives.v here
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Transmission gates tran and rtran are permanently on and do not have a control line. Tran can be used to interface two wires with separate drives, and rtran can be used to weaken signals. Resistive devices reduce the signal strength which appears on the output by one level. All the switches only pass signals from source to drain, incorrect wiring of the devices will result in high impedance outputs. |
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Logic Values and signal Strengths
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The Verilog HDL has got four logic values |
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Logic Value
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Description
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0
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zero, low, false
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1
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one, high, true
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z or Z
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high impedance, floating
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x or X
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unknown, uninitialized, contention
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Verilog Strength Levels
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Strength Level
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Specification Keyword
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7 Supply Drive
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supply0 supply1
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6 Strong Pull
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strong0 strong1
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5 Pull Drive
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pull0 pull1
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4 Large Capacitance
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large
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3 Weak Drive
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weak0 weak1
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2 Medium Capacitance
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medium
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1 Small Capacitance
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small
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0 Hi Impedance
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highz0 highz1
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Example : Strength Level
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Two buffers that has output |
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A : Pull 1 |
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B : Supply 0 |
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Since supply 0 is stronger then pull 1, Output C takes value of B. |
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Example 2 : Strength Level
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Two buffers that has output |
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A : Supply 1 |
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B : Large 1 |
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Since Supply 1 is stronger then Large 1, Output C takes the value of A |
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