A compiler directive may be used to control the compilation of a Verilog description. The grave accent mark, `, denotes a compiler directive. A directive is effective from the point at which it is declared to the point at which another directive overrides it, even across file boundaries. Compiler directives may appear anywhere in the source description, but it is recommended that they appear outside a module declaration. This appendix presents those directives that are part of IEEE-1364.

As in any language, each compiler has its own way of handling command line options and supported compiler directives in code. Below we will see some standard and common compiler directives. For specific compiler directives, please refer to simulator manuals.

The `include compiler directive lets you insert the entire contents of a source file into another file during Verilog compilation. The compilation proceeds as though the contents of the included source file appear in place of the `include command. You can use the `include compiler directive to include global or commonly-used definitions and tasks, without encapsulating repeated code within module boundaries.

This compiler directive is used for defining text MACROS; this is normally defined in verilog file "name.vh", where name can be the module that you are coding. Since `define is compiler directive, it can be used across multiple files.

The `undef compiler directive lets you remove definitions of text macros created by the `define compiler directive and the +define+ command-line plus option. You can use the `undef compiler directive to undefine a text macro that you use in more than one file.

Optionally includes lines of source code during compilation. The `ifdef directive checks that a macro has been defined, and if so, compiles the code that follows. If the macro has not been defined, the compiler compiles the code (if any) following the optional `else directive. You can control what code is compiled by choosing whether to define the text macro, either with `define or with +define+. The `endif directive marks the end of the conditional code.

  1 module ifdef ();
  2 
  3 initial begin
  4 `ifdef FIRST
  5     $display("First code is compiled");
  6 `else
  7   `ifdef SECOND 
  8     $display("Second code is compiled");
  9   `else
 10     $display("Default code is compiled");
 11   `endif
 12 `endif
 13   $finish;
 14 end
 15 
 16 endmodule

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