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  ../images/main/bulllet_4dots_orange.gif not tran

The not trans specification is another special case for transition bins that causes Vera to record undefined transitions without print a verification error.

   

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tran tran_bin_name (not tran);

   

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  ../images/main/bullet_star_pink.gif Example
   

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  1 class coverage_no_tran {
  2   bit [3:0] value;
  3   event     now;
  4 
  5   coverage_group something {
  6      sample_event = sync(ALL,now);
  7      sample value {
  8       trans ABC_0 (2->5);
  9       trans ABC_1 (3->5);
 10       trans ABC_2 (4->5);
 11       trans ABC_3 (6->5);
 12       trans ABC_4 (7->5);
 13       trans ABC_INVALID (not trans);
 14      }
 15   }
 16 
 17   task update_coverage (bit [3:0] value) {
 18      this.value = value;
 19      trigger(now);
 20   }
 21 }
 22 
 23 
 24 
 25 program test {
 26   coverage_no_tran cov = new();
 27   bit [3:0] v; 
 28   repeat (10) {
 29     v = urandom__range(14,0);
 30     printf("Value is %d\n",v);
 31     cov.update_coverage(v);
 32     @ (posedge CLOCK);
 33   }
 34 }    
You could download file coverage_no_tran.vr here
   

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  ../images/main/bullet_star_pink.gif Simulation log
   

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 Value is 13
 Value is 14
 Value is  4
 Value is  4
 Value is  2
 Value is  8
 Value is  6
 Value is  7
 Value is  6
 Value is  2
   

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  ../images/main/bullet_star_pink.gif Coverage Report
   

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 Group : test::coverage_no_tran::something
 
 ====================================================
 Group : test::coverage_no_tran::something
 ====================================================
 Score   Weight  Goal    
  16.67  1       100     
 
 
 
 
 ====================================================
 
 Samples for Group : test::coverage_no_tran::something
 
 
 
 Variable Expected Covered Percent Goal Weight 
                                               
 Total    6        1       16.67               
                                               
 value    6        1       16.67   100  1      
                                               
 
 
 ====================================================
 
 Summary for variable value
 
 
                   Expected Covered Percent 
                                            
 User Defined Bins 6        1       16.67   
                                            
 
 
 User Defined Bins for value
 
 
 Uncovered bins
 
 name  count at least  
                      
 ABC_4 0     1        
                      
 ABC_3 0     1        
                      
 ABC_2 0     1        
                      
 ABC_1 0     1        
                      
 ABC_0 0     1        
                      
 
 
 Covered bins
 
 name        count at least  
                            
 ABC_INVALID 9     1        
                            
 
 
   

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Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

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