Use the m_trans transition declaration to declare multiple transition bins up to a maximum of 4096 bins.

The syntax is:

m_trans trans_bin_name (exp1:exp2 -> exp3:exp4);

• trans_bin_name : is the base name of the transition bins being created.
• exp : can be any valid coverage expression. You cannot call functions in the expressions, but they can include variables that are visible in the scope of the coverage group.

When you use an m_trans declaration, Vera creates multiple transition bins that cover all transitions in the specified ranges. Each set of expressions specifies a range

  1 class coverage_m_tran {
  2   bit [3:0] value;
  3   event     now;
  4 
  5   coverage_group something {
  6      sample_event = sync(ALL,now);
  7      sample value {
  8       m_trans(2:5->6:14);
  9      }
 10   }
 11 
 12   task update_coverage (bit [3:0] value) {
 13      this.value = value;
 14      trigger(now);
 15   }
 16 }
 17 
 18 
 19 
 20 program test {
 21   coverage_m_tran cov = new();
 22   bit [3:0] v; 
 23   repeat (10) {
 24     v = urandom__range(14,0);
 25     printf("Value is %d\n",v);
 26     cov.update_coverage(v);
 27     delay(1);
 28   }
 29 }    

 Value is 13
 Value is 14
 Value is  4
 Value is  4
 Value is  2
 Value is  8
 Value is  6
 Value is  7
 Value is  6
 Value is  2

 Group : test::coverage_m_tran::something
 
 ====================================================
 Group : test::coverage_m_tran::something
 ====================================================
 Score   Weight  Goal    
   2.78  1       100     
 
 
 
 
 ====================================================
 
 Samples for Group : test::coverage_m_tran::something
 
 
 
 Variable Expected Covered Percent Goal Weight 
                                               
 Total    36       1       2.78                
                                               
 value    36       1       2.78    100  1      
                                               
 
 
 ====================================================
 
 Summary for variable value
 
 
                   Expected Covered Percent 
                                            
 User Defined Bins 36       1       2.78    
                                            
 
 
 User Defined Bins for value
 
 
 Uncovered bins
 
 name                 count at least  
                                     
 t_s_2_5_s_6_14:2->6  0     1        
                                     
 t_s_2_5_s_6_14:3->6  0     1        
                                     
 t_s_2_5_s_6_14:4->6  0     1        
                                     
 t_s_2_5_s_6_14:5->6  0     1        
                                     
 t_s_2_5_s_6_14:2->7  0     1        
                                     
 t_s_2_5_s_6_14:3->7  0     1        
                                     
 t_s_2_5_s_6_14:4->7  0     1        
                                     
 t_s_2_5_s_6_14:5->7  0     1        
                                     
 t_s_2_5_s_6_14:3->8  0     1        
                                     
 t_s_2_5_s_6_14:4->8  0     1        
                                     
 t_s_2_5_s_6_14:5->8  0     1        
                                     
 t_s_2_5_s_6_14:2->9  0     1        
                                     
 t_s_2_5_s_6_14:3->9  0     1        
                                     
 t_s_2_5_s_6_14:4->9  0     1        
                                     
 t_s_2_5_s_6_14:5->9  0     1        
                                     
 t_s_2_5_s_6_14:2->10 0     1        
                                     
 t_s_2_5_s_6_14:3->10 0     1        
                                     
 t_s_2_5_s_6_14:4->10 0     1        
                                     
 t_s_2_5_s_6_14:5->10 0     1        
                                     
 t_s_2_5_s_6_14:2->11 0     1        
                                     
 t_s_2_5_s_6_14:3->11 0     1        
                                     
 t_s_2_5_s_6_14:4->11 0     1        
                                     
 t_s_2_5_s_6_14:5->11 0     1        
                                     
 t_s_2_5_s_6_14:2->12 0     1        
                                     
 t_s_2_5_s_6_14:3->12 0     1        
                                     
 t_s_2_5_s_6_14:4->12 0     1        
                                     
 t_s_2_5_s_6_14:5->12 0     1        
                                     
 t_s_2_5_s_6_14:2->13 0     1        
                                     
 t_s_2_5_s_6_14:3->13 0     1        
                                     
 t_s_2_5_s_6_14:4->13 0     1        
                                     
 t_s_2_5_s_6_14:5->13 0     1        
                                     
 t_s_2_5_s_6_14:2->14 0     1        
                                     
 t_s_2_5_s_6_14:3->14 0     1        
                                     
 t_s_2_5_s_6_14:4->14 0     1        
                                     
 t_s_2_5_s_6_14:5->14 0     1        
                                     
 
 
 Covered bins
 
 name                count at least  
                                    
 t_s_2_5_s_6_14:2->8 1     1        
                                    
 
 

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