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  ../images/main/bulllet_4dots_orange.gif Event control

Verilog event control contains with @, delay with #. SystemVerilog improves upon this and added following

   

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  • @ *
  • @ (*)
  • event expression , iff
   

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While modeling combo logic or anything that is sensitive to level, in Verilog it is necessary to type all the variabled in LHS in sensitive list. In SystemVerilog we can use @ (*) instead.

   

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SystemVerilog addes one more important reserve word iff, what this does is a event is triggered only if condition after iff hold true.

   

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Example : always @ (posedge clk iff reset == 0 or posedge reset)

   

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What this does is when reset is high, block does not get triggered.

   

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  ../images/main/bullet_star_pink.gif Example - Event Control
   

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  1 module event_control ();
  2 
  3 reg clk = 0;
  4 reg rst, d, enable, q, latch;
  5 
  6 
  7 always @ (*)
  8 if (enable) begin
  9    latch <= d;
 10 end
 11 
 12 always @ (posedge clk iff rst == 0 or posedge rst)
 13 if (rst) begin
 14   q <= 0;
 15   $display ("Reset is asserted with iff");
 16 end else begin
 17   q <= d;
 18 end
 19 
 20 always @ (posedge clk or posedge rst)
 21 if (rst) begin
 22   $display ("Reset is asserted, no iff");
 23 end
 24 
 25 always  #1  clk = ~clk; 
 26 
 27 
 28 initial begin
 29  $monitor ("@%g clk %b rst %b enable %b d %b q %b latch %b",
 30             $time, clk, rst, enable, d, q, latch);
 31  rst = 0;
 32   #1  d = 0;
 33   #1  rst = 1;
 34   #4  rst = 0;
 35   #1  enable = 1;
 36   #1  d = 1;
 37   #10  d = 0;
 38   #5  $finish;
 39 end
 40 
 41 endmodule
You could download file event_control.sv here
   

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Simulator Output

   

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 @0 clk 0 rst 0 enable x d x q x latch x
 @1 clk 1 rst 0 enable x d 0 q 0 latch x
 Reset is asserted with iff
 Reset is asserted, no iff
 @2 clk 0 rst 1 enable x d 0 q 0 latch x
 Reset is asserted, no iff
 @3 clk 1 rst 1 enable x d 0 q 0 latch x
 @4 clk 0 rst 1 enable x d 0 q 0 latch x
 Reset is asserted, no iff
 @5 clk 1 rst 1 enable x d 0 q 0 latch x
 @6 clk 0 rst 0 enable x d 0 q 0 latch x
 @7 clk 1 rst 0 enable 1 d 0 q 0 latch 0
 @8 clk 0 rst 0 enable 1 d 1 q 0 latch 1
 @9 clk 1 rst 0 enable 1 d 1 q 1 latch 1
 @10 clk 0 rst 0 enable 1 d 1 q 1 latch 1
 @11 clk 1 rst 0 enable 1 d 1 q 1 latch 1
 @12 clk 0 rst 0 enable 1 d 1 q 1 latch 1
 @13 clk 1 rst 0 enable 1 d 1 q 1 latch 1
 @14 clk 0 rst 0 enable 1 d 1 q 1 latch 1
 @15 clk 1 rst 0 enable 1 d 1 q 1 latch 1
 @16 clk 0 rst 0 enable 1 d 1 q 1 latch 1
 @17 clk 1 rst 0 enable 1 d 1 q 1 latch 1
 @18 clk 0 rst 0 enable 1 d 0 q 1 latch 0
 @19 clk 1 rst 0 enable 1 d 0 q 0 latch 0
 @20 clk 0 rst 0 enable 1 d 0 q 0 latch 0
 @21 clk 1 rst 0 enable 1 d 0 q 0 latch 0
 @22 clk 0 rst 0 enable 1 d 0 q 0 latch 0
   

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  ../images/main/bulllet_4dots_orange.gif Sequence

A sequence instance can be used in event expressions to control the execution of procedural statements based on the successful match of the sequence. A sequence instance can be used directly in an event expression. We will see more of sequence in SystemVerilog Assertions section.

   

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  ../images/main/bullet_star_pink.gif Example - Event sequence
   

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  1 module sequence_event ();
  2 
  3 reg a, b, c;
  4 reg clk = 0;
  5 
  6 sequence abc; 
  7   @(posedge clk) a  ##1  b  ##1  c; 
  8 endsequence
  9 
 10 always @ (posedge clk)
 11 begin
 12  @ (abc) $display ("@%g ABC all are asserted", $time);
 13 end
 14 
 15 // Testbench code
 16 initial begin
 17   $monitor("@%g clk %b a %b b %b c %b", $time, clk, a, b, c); 
 18   repeat (2) begin
 19      #2  a = 1;
 20      #2  b = 1;
 21      #2  c = 1;
 22      #2  a = 0;
 23     b = 0;
 24     c = 0;
 25   end
 26    #2  $finish;
 27 end
 28 
 29 always  #1  clk = ~clk;
 30 
 31 endmodule
You could download file sequence_event.sv here
   

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Simulator Output

   

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 @0 clk 0 a x b x c x
 @1 clk 1 a x b x c x
 @2 clk 0 a 1 b x c x
 @3 clk 1 a 1 b x c x
 @4 clk 0 a 1 b 1 c x
 @5 clk 1 a 1 b 1 c x
 @6 clk 0 a 1 b 1 c 1
 @7 ABC all are asserted
 @7 clk 1 a 1 b 1 c 1
 @8 clk 0 a 0 b 0 c 0
 @9 clk 1 a 0 b 0 c 0
 @10 clk 0 a 1 b 0 c 0
 @11 clk 1 a 1 b 0 c 0
 @12 clk 0 a 1 b 1 c 0
 @13 clk 1 a 1 b 1 c 0
 @14 clk 0 a 1 b 1 c 1
 @15 ABC all are asserted
 @15 clk 1 a 1 b 1 c 1
 @16 clk 0 a 0 b 0 c 0
 @17 clk 1 a 0 b 0 c 0
   

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  ../images/main/bulllet_4dots_orange.gif Level-sensitive sequence controls

The execution of procedural code can be delayed until a sequence termination status is true. This is accomplished using the level-sensitive wait statement in conjunction with the built-in method that returns the current end status of a named sequence: triggered.

   

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  ../images/main/bullet_star_pink.gif Example - Level Sensitive
   

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  1 module sequence_wait ();
  2 
  3 reg a, b, c, d, e;
  4 reg clk = 0;
  5 
  6 sequence abc; 
  7   @(posedge clk) a  ##1  b  ##1  c; 
  8 endsequence 
  9 
 10 sequence de; 
 11   @(negedge clk) d ##[2:5] e; 
 12 endsequence 
 13 
 14 initial begin 
 15   forever begin
 16     wait (abc.triggered || de.triggered); 
 17     if (abc.triggered) begin
 18       $display( "@%g abc succeeded", $time ); 
 19     end
 20     if (de.triggered) begin
 21       $display( "@%g de succeeded", $time );
 22     end
 23      #2 ;
 24   end
 25 end
 26 
 27 // Testbench code
 28 initial begin
 29   $monitor("@%g clk %b a %b b %b c %b d %b e %b", $time, clk, a, b, c, d, e); 
 30   repeat (2) begin
 31      #2  a = 1;
 32     d = 1;
 33      #2  b = 1;
 34     e = 1;
 35      #2  c = 1;
 36      #2  a = 0;
 37     b = 0;
 38     c = 0;
 39     e = 0;
 40   end
 41    #2  $finish;
 42 end
 43 
 44 always  #1  clk = ~clk;
 45 
 46 endmodule
You could download file sequence_wait.sv here
   

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Simulator Output

   

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 @0 clk 0 a x b x c x d x e x
 @1 clk 1 a x b x c x d x e x
 @2 clk 0 a 1 b x c x d 1 e x
 @3 clk 1 a 1 b x c x d 1 e x
 @4 clk 0 a 1 b 1 c x d 1 e 1
 @5 clk 1 a 1 b 1 c x d 1 e 1
 @6 clk 0 a 1 b 1 c 1 d 1 e 1
 @7 abc succeeded
 @7 clk 1 a 1 b 1 c 1 d 1 e 1
 @8 clk 0 a 0 b 0 c 0 d 1 e 0
 @9 clk 1 a 0 b 0 c 0 d 1 e 0
 @10 clk 0 a 1 b 0 c 0 d 1 e 0
 @11 clk 1 a 1 b 0 c 0 d 1 e 0
 @12 clk 0 a 1 b 1 c 0 d 1 e 1
 @13 clk 1 a 1 b 1 c 0 d 1 e 1
 @14 de succeeded
 @14 clk 0 a 1 b 1 c 1 d 1 e 1
 @15 clk 1 a 1 b 1 c 1 d 1 e 1
 @16 de succeeded
 @16 clk 0 a 0 b 0 c 0 d 1 e 0
 @17 clk 1 a 0 b 0 c 0 d 1 e 0
   

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Deepak Kumar Tala - All rights reserved

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