Named blocks in Verilog are allowed for begin and fork. They can be added only after the reserver word begin and fork as shown below

• begin : "MY_NAMED_BLOCK1"
• fork : "MY_NAMED_BLOCK2"

SystemVerilog extends it and allows one to add named blocks to reserve word end and join. Also SystemVerilog allows to add the LABLE or NAMED BLOCK before begin, fork as below.

• "MY_NAMED_BLOCK" : begin
• "MY_NAMED_BLOCK" : end
• "MY_NAMED_BLOCK" : fork
• "MY_NAMED_BLOCK" : join

It is illegal to have both a label before a begin or fork and a block name after the begin or fork. A label cannot appear before the end, join, join_any or join_none, as these keywords do not form a statement.

  1 module named_block ();
  2 
  3 reg clk = 0;
  4 
  5 initial
  6  FIRST_BLOCK : begin
  7    $display ("This is first block");  
  8  end 
  9 
 10 initial begin : SECOND_BLOCK
 11    $display ("This is second block"); 
 12    fork : FORK_BLOCK
 13       #1  $display ("Inside fork with delay 1");
 14       #2  $display ("Inside fork with delay 2");
 15    join_none 
 16    FORK_NONE : fork
 17       #4  $display ("Inside fork with delay 4");
 18       #5  $display ("Inside fork with delay 5");
 19    join_none 
 20     #10  $finish;
 21 end
 22 
 23 always begin  : THIRD_BLOCK
 24   #1  clk = ~clk;
 25 end : THIRD_BLOCK
 26 
 27 endmodule

Simulator Output

 This is first block
 This is second block
 Inside fork with delay 1
 Inside fork with delay 2
 Inside fork with delay 4
 Inside fork with delay 5

SystemVerilog has break and continue to break out of or continue the execution of loops. The Verilog-2001 disable can also be used to break out of or continue a loop, but is more awkward than using break or conseq_ Accellera Extensions to Verilog-2001 SystemVerilog 3.1a tinue. The disable is also allowed to disable a named block, which does not contain the disable statement. If the block is currently executing, this causes control to jump to the statement immediately after the block. If the block is a loop body, it acts like a continue. If the block is not currently executing, the disable has no effect.

It is good idea to stick to using continue or break for stopping executing of a block of code. But then if one he used to using disable statement, then SystemVerilog allows one to use it too.

  1 module disable_block ();
  2 
  3 initial begin
  4   fork : FORK
  5     for (int i = 0 ; i < 9; i ++) begin
  6       if (1 == 5) begin
  7         $display ("break first for loop");
  8         break;
  9       end
 10        #1  $display ("First  -> Current value of i = %g", i);
 11     end
 12     for (int i = 9 ; i > 0; i --) begin : FOR_LOOP
 13       if (i == 6) begin
 14         $display ("Disable FOR_LOOP");
 15         disable FOR_LOOP;
 16       end
 17        #1  $display ("Second -> Current value of i = %g", i);
 18     end
 19     for (int i = 0 ; i < 30; i += 2) begin : FOR_LOOP
 20       if (i == 16) begin
 21         $display ("Disable FORK");
 22         disable FORK;
 23       end
 24        #1  $display ("third -> Current value of i = %g", i);
 25     end
 26   join
 27    #10  $finish;
 28 end
 29 
 30 endmodule

Simulator Output

 First  -> Current value of i = 0
 Second -> Current value of i = 9
 third -> Current value of i = 0
 First  -> Current value of i = 1
 Second -> Current value of i = 8
 third -> Current value of i = 2
 First  -> Current value of i = 2
 Second -> Current value of i = 7
 Disable FOR_LOOP
 third -> Current value of i = 4
 First  -> Current value of i = 3
 Second -> Current value of i = 5
 third -> Current value of i = 6
 First  -> Current value of i = 4
 Second -> Current value of i = 4
 third -> Current value of i = 8
 First  -> Current value of i = 5
 Second -> Current value of i = 3
 third -> Current value of i = 10
 First  -> Current value of i = 6
 Second -> Current value of i = 2
 third -> Current value of i = 12
 First  -> Current value of i = 7
 Second -> Current value of i = 1
 third -> Current value of i = 14
 Disable FORK

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Deepak Kumar Tala - All rights reserved

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