The name $root is added to unambiguously refer to a top-level instance or to an instance path starting from the root of the instantiation tree. $root is the root of the instantiation tree. In Verilog, a hierarchical path is ambiguous.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 // Child Module
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module child();
  5 
  6 //=================================================
  7 // Method inside child
  8 //=================================================
  9 task print();
 10  $display("%m : Inside Module child");
 11 endtask 
 12 
 13 initial begin
 14   $root.top.U.U.print();
 15 end
 16 
 17 endmodule
 18 
 19 
 20 //+++++++++++++++++++++++++++++++++++++++++++++++++
 21 // Parent Module
 22 //+++++++++++++++++++++++++++++++++++++++++++++++++
 23 module parent();
 24 
 25 //=================================================
 26 // Method inside parent
 27 //=================================================
 28 task print();
 29  $display("%m : Inside Module praent");
 30 endtask 
 31 
 32 child U ();
 33 
 34 initial begin
 35   $root.top.U2.print();
 36   $root.top.U.print();
 37 end
 38 
 39 endmodule
 40 
 41 //+++++++++++++++++++++++++++++++++++++++++++++++++
 42 // Top Module
 43 //+++++++++++++++++++++++++++++++++++++++++++++++++
 44 module top();
 45 
 46 parent U();
 47 child U2();
 48 
 49 //=================================================
 50 // Method inside top
 51 //=================================================
 52 task print();
 53  $display("%m : Inside Module top");
 54 endtask 
 55 
 56 endmodule

 top.U.U.print : Inside Module child
 top.U2.print : Inside Module child
 top.U.print : Inside Module praent
 top.U.U.print : Inside Module child

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