In Verilog 2001 and 1995, module declaration inside another module is not allowed, only modules can be instanciated. But in SystemVerilog, module declaration can be nested.The outer name space is visible to the inner module so that any name declared there can be used, unless hidden by a local name, provided the module is declared and instantiated in the same scope.

One purpose of nesting modules is to show the logical partitioning of a module without using ports. Names that are global are in the outermost scope, and names that are only used locally can be limited to local modules.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 // Nested Module
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module nested_module();
  5 
  6 //=================================================
  7 // Module declration inside the module 
  8 //=================================================
  9 module counter(input clk,enable,reset, 
 10 output logic [3:0] data);
 11 
 12   always @ (posedge clk)
 13     if (reset) data <= 0;
 14     else if (enable) data ++;
 15 endmodule
 16 
 17 logic clk = 0;
 18 always  #1  clk++;
 19 logic enable, reset;
 20 wire [3:0] data;
 21 
 22 counter U(clk,enable,reset,data);
 23 
 24 initial begin
 25   $monitor("@%0dns reset %b enable %b data %b",
 26      $time,reset,enable,data);
 27   reset <= 1;
 28    #10  reset <= 0;
 29    #1  enable <= 1;
 30    #10  enable <= 0;
 31    #4  $finish;
 32 end
 33 
 34 endmodule

 @0ns reset 1 enable x data xxxx
 @1ns reset 1 enable x data 0000
 @10ns reset 0 enable x data 0000
 @11ns reset 0 enable 1 data 0000
 @13ns reset 0 enable 1 data 0001
 @15ns reset 0 enable 1 data 0010
 @17ns reset 0 enable 1 data 0011
 @19ns reset 0 enable 1 data 0100
 @21ns reset 0 enable 0 data 0101

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Deepak Kumar Tala - All rights reserved

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