Like Verilog memories, the dimensions following the type set the packed size. The dimensions following the instance set the unpacked size. As in Verilog-2001, a comma-separated list of array declarations can be made. All arrays in the list shall have the same data type and the same packed array dimensions.

SystemVerilog uses the term part select to refer to a selection of one or more contiguous bits of a single dimension packed array. This is consistent with the usage of the term part select in Verilog. SystemVerilog uses the term slice to refer to a selection of one or more contiguous elements of an array. Verilog only permits a single element of an array to be selected, and does not have a term for this selection.

  1 module arrays_data();
  2 
  3 // 2 dimension array of Verilog 2001
  4 reg [7:0] mem [0:3] = '{8'h0,8'h1,8'h2,8'h3};
  5 // one more example of multi dimention array
  6 reg [7:0] mem1 [0:1] [0:3] = 
  7    '{'{8'h0,8'h1,8'h2,8'h3},'{8'h4,8'h5,8'h6,8'h7}};
  8 // One more example of multi dimention array
  9 reg [7:0] [0:4] mem2 [0:1] = 
 10    '{{8'h0,8'h1,8'h2,8'h3},{8'h4,8'h5,8'h6,8'h7}};
 11 // One more example of multi dimention array
 12 reg [7:0] [0:4] mem3 [0:1] [0:1]  = 
 13    '{'{{8'h0,8'h1,8'h2,8'h3},{8'h4,8'h5,8'h6,8'h7}},
 14    '{{8'h0,8'h1,8'h2,8'h3},{8'h4,8'h5,8'h6,8'h7}}};
 15 // Multi arrays in same line declaration
 16 bit [7:0] [31:0] mem4 [1:5] [1:10], mem5 [0:255]; 
 17 
 18 initial begin
 19   $display ("mem[0]            = %b", mem[0]);
 20   $display ("mem[1][0]         = %b", mem[1][0]);
 21   $display ("mem1[0][1]        = %b", mem1[0][1]);
 22   $display ("mem1[1][1]        = %b", mem1[1][1]);
 23    #1  $finish;
 24 end
 25 
 26 endmodule

 mem[0]            = 00000000
 mem[1][0]         = 1
 mem1[0][1]        = 00000001
 mem1[1][1]        = 00000101

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