An array is a collection of variables, all of the same type, and accessed using the same name plus one or more indices.

In C, arrays are indexed from 0 by integers, or converted to pointers. Although the whole array can be initialized, each element must be read or written separately in procedural statements.

In Verilog-2001, arrays are indexed from left-bound to right-bound. If they are vectors, they can be assigned as a single unit, but not if they are arrays. Verilog-2001 allows multiple dimensions.

In Verilog-2001, all data types can be declared as arrays. The reg, wire and all other net types can also have a vector width declared. A dimension declared before the object name is referred to as the "vector width" dimension. The dimensions declared after the object name are referred to as the "array" dimensions.

SystemVerilog uses the term packed array to refer to the dimensions declared before the object name (what Verilog-2001 refers to as the vector width). The term unpacked array is used to refer to the dimensions declared after the object name.

Packed arrays can only be made of the single bit types (bit, logic, reg, wire, and the other net types) and recursively other packed arrays and packed structures. The maximum size of a packed array can be limited, but shall be at least 65536 (216) bits.

  1 module packed_unpacked_data();
  2 
  3 // packed array
  4 bit [7:0] packed_array = 8'hAA; 
  5 // unpacked array
  6 reg unpacked_array [7:0] = '{0,0,0,0,0,0,0,1}; 
  7 
  8 initial begin
  9   $display ("packed array[0]   = %b", packed_array[0]);
 10   $display ("unpacked array[0] = %b", unpacked_array[0]);
 11   $display ("packed array      = %b", packed_array);
 12   // Below one is wrong syntax
 13   //$display("unpacked array[0] = %b",unpacked_array);
 14    #1  $finish;
 15 end
 16 
 17 endmodule

 packed array[0]   = 0
 unpacked array[0] = 1
 packed array      = 10101010

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