Normally coverage groups are coded to work on known variables, Like addres, data, or response. There are times when we don't want the coverage group to be generic, so that same coverage group can be instanciated multiple times, and each instance working on its own set of variables.

Generic coverage group is created by passing variable traits as arguments, just like we do for function and task

   1 //+++++++++++++++++++++++++++++++++++++++++++++++++
   2 // Define the interface with coverage
   3 //+++++++++++++++++++++++++++++++++++++++++++++++++
   4 interface mem_if (input wire clk);
   5   logic       reset;
   6   logic       we;
   7   logic       ce;
   8   logic [7:0] datai;
   9   logic [7:0] datao;
  10   logic [7:0] addr;
  11   //=================================================
  12   // Clocking block for testbench
  13   //=================================================
  14   clocking cb @ (posedge clk);
  15     output reset, we, ce, datai,addr;
  16     input  datao;
  17   endclocking
  18   //=================================================
  19   // Coverage Group in interface
  20   //=================================================
  21   covergroup address_cov (ref logic [7:0] address,
  22        input int low, int high) @ (posedge ce);
  23     ADDRESS : coverpoint address {
  24       bins low    = {0,low};
  25       bins med    = {low,high};
  26     }
  27   endgroup
  28   //=================================================
  29   // Instance of covergroup
  30   //=================================================
  31   address_cov acov_low  = new(addr,0,10);
  32   address_cov acov_med  = new(addr,11,20);
  33   address_cov acov_high = new(addr,21,30);
  34 
  35 endinterface
  36 //+++++++++++++++++++++++++++++++++++++++++++++++++
  37 //   DUT With interface
  38 //+++++++++++++++++++++++++++++++++++++++++++++++++
  39 module simple_if (mem_if mif);
  40 // Memory array
  41 logic [7:0] mem [0:255];
  42 
  43 //=================================================
  44 // Read logic
  45 //=================================================
  46 always @ (posedge mif.clk)
  47  if (mif.reset) mif.datao <= 0;
  48  else if (mif.ce &&  ! mif.we) mif.datao <= mem[mif.addr];
  49 
  50 //=================================================
  51 // Write Logic
  52 //=================================================
  53 always @ (posedge mif.clk)
  54  if (mif.ce && mif.we) mem[mif.addr] <= mif.datai;
  55 
  56 endmodule
  57 
  58 //+++++++++++++++++++++++++++++++++++++++++++++++++
  59 //  Testbench
  60 //+++++++++++++++++++++++++++++++++++++++++++++++++
  61 module coverage_covergroup();
  62 
  63 logic clk = 0;
  64 always  #10  clk++;
  65 //=================================================
  66 // Instianciate Interface and DUT 
  67 //=================================================
  68 mem_if miff(clk);
  69 simple_if U_dut(miff);
  70 //=================================================
  71 // Default clocking  
  72 //=================================================
  73 default clocking dclk @ (posedge clk);
  74 
  75 endclocking
  76 //=================================================
  77 // Test Vector generation
  78 //=================================================
  79 initial begin
  80   miff.reset     <= 1;
  81   miff.ce        <= 1'b0;
  82   miff.we        <= 1'b0;
  83   miff.addr      <= 0;
  84   miff.datai     <= 0;
  85    ##1  miff.reset <= 0;
  86   for (int i = 0; i < 3; i ++ ) begin
  87      ##1  miff.ce  <= 1'b1;
  88     miff.we      <= 1'b1;
  89     miff.addr    <= i;
  90     miff.datai   <= $random;
  91      ##3  miff.ce  <= 1'b0;
  92     $display ("@%0dns Write access address %x, data %x",
  93       $time,miff.addr,miff.datai);
  94   end
  95   for (int i = 0; i < 3; i ++ ) begin
  96      ##1  miff.ce  <= 1'b1;
  97     miff.we      <= 1'b0;
  98     miff.addr    <= i;
  99      ##3  miff.ce  <= 1'b0;
 100     $display ("@%0dns Read access address %x, data %x",
 101       $time,miff.addr,miff.datao);
 102   end
 103    #10  $finish;
 104 end
 105 
 106 endmodule

 @90ns Write access address 00, data 24
 @170ns Write access address 01, data 81
 @250ns Write access address 02, data 09
 @330ns Read access address 00, data 24
 @410ns Read access address 01, data 81
 @490ns Read access address 02, data 09

 ===========================================================
 Group : coverage_covergroup.miff::address_cov
 ===========================================================
 SCORE  WEIGHT GOAL   
 100.00 1      100    
 -----------------------------------------------------------
 Summary for Group   coverage_covergroup.miff::address_cov
 CATEGORY  EXPECTED UNCOVERED COVERED PERCENT 
 Variables 2        0         2       100.00  
 
 Variables for Group  coverage_covergroup.miff::address_cov
 
 VARIABLE EXPECTED UNCOVERED COVERED PERCENT GOAL WEIGHT 
 ADDRESS  2        0         2       100.00  100  1      
 -----------------------------------------------------------
 Summary for Variable ADDRESS
 
 CATEGORY          EXPECTED UNCOVERED COVERED PERCENT 
 User Defined Bins 2        0         2       100.00  
 
 User Defined Bins for ADDRESS
 Bins
 
 NAME COUNT AT LEAST  
 med  2     1        
 low  6     1        

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Deepak Kumar Tala - All rights reserved

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