| |
|
|
|
|
|
| |
|
|
| |
 |
Coverage Points
|
|
|
A covergroup can contain one or more coverage points. A coverage point can be an integral variable or an integral expression. Each coverage point includes a set of bins associated with its sampled values or its value transitions. The bins can be explicitly defined by the user or automatically created by SystemVerilog. A coverage point creates a hierarchical scope and can be optionally labeled. If the label is specified, then it designates the name of the coverage point. This name can be used to add this coverage point to a cross coverage specification or to access the methods of the coverage point. If the label is omitted and the coverage point is associated with a single variable, then the variable name becomes the name of the coverage point. Otherwise, an implementation can generate a name for the coverage point only for the purposes of coverage reporting, that is, generated names cannot be used within the language. |
| |
|
|
|
|
Coverage point can contain optional iff statement to disable the coverage collection, when condition is active, say reset is asserted and we don't want to collect coverage during reset. |
| |
|
|
|
|
A coverage point bin associates a name and a count with a set of values or a sequence of value transitions. If the bin designates a set of values, the count is incremented every time the coverage point matches one of the values in the set. If the bin designates a sequence of value transitions, the count is incremented every time the coverage point matches the entire sequence of value transitions. |
| |
|
|
|
|
The bins for a coverage point can be automatically created by SystemVerilog or explicitly defined using the bins construct to name each bin. If the bins are not explicitly defined, they are automatically created by SystemVerilog. The number of automatically created bins can be controlled using the auto_bin_max coverage option. |
| |
|
|
|
|
The bins construct allows creating a separate bin for each value in the given range list or a single bin for the entire range of values. To create a separate bin for each value (an array of bins), the square brackets, [], must follow the bin name. To create a fixed number of bins for a set of values, a number can be specified inside the square brackets. The open_range_list used to specify the set of values associated with a bin shall be constant expressions, instance constants (for classes only), or non-ref arguments to the coverage group. It shall be legal to use the $ primary in an open_value_range of the form [ expression : $ ] or [ $ : expression ]. |
| |
|
|
|
|
If a fixed number of bins is specified and that number is smaller than the specified number of values, then the possible bin values are uniformly distributed among the specified bins. |
| |
|
|
|
|
The expression within the iff construct at the end of a bin definition provides a per-bin guard condition. If the expression is false at a sampling point, the count for the bin is not incremented. |
| |
|
|
|
|
The default specification defines a bin that is associated with none of the defined value bins. The default bin catches the values of the coverage point that do not lie within any of the defined bins. However, the coverage calculation for a coverage point shall not take into account the coverage captured by the default bin. The default bin is also excluded from cross coverage The default sequence form can be used to catch all transitions (or sequences) that do not lie within any of the defined transition bins. The default sequence specification does not accept multiple transition bins (i.e., the [] notation is not allowed). |
| |
|
|
| |
 |
Example : Coverage Points
|
| |
|
|
|
|
1 //+++++++++++++++++++++++++++++++++++++++++++++++++
2 // Define the interface with coverage
3 //+++++++++++++++++++++++++++++++++++++++++++++++++
4 interface mem_if (input wire clk);
5 wire reset;
6 wire we;
7 wire ce;
8 wire [7:0] datai;
9 logic [7:0] datao;
10 wire [7:0] addr;
11 //=================================================
12 // Clocking block for testbench
13 //=================================================
14 clocking cb @ (posedge clk);
15 output reset, we, ce, datai,addr;
16 input datao;
17 endclocking
18 //=================================================
19 // Modport for testbench
20 //=================================================
21 modport tb (clocking cb, input clk);
22
23 //=================================================
24 // Coverage Group in interface
25 //=================================================
26 covergroup memory @ (posedge ce);
27 // Cover only if reset is high
28 address : coverpoint addr iff (miff.reset) {
29 bins low = {0,50};
30 bins med [] = {51,100};
31 bins high = {101,150};
32 bins others[] = default;
33 }
34 data_in : coverpoint datai {
35 bins low = {0,50};
36 bins med = {[51:100],[60:150]};
37 bins high = {151,255};
38 bins med_end= {[51:$]};
39 }
40 data_out : coverpoint datao {
41 bins low = {0,50};
42 bins med = {51,150};
43 bins high = {151,255};
44 }
45 read_write : coverpoint we {
46 bins read = {0};
47 bins write = {1};
48 }
49 endgroup
50 //=================================================
51 // Instance of covergroup
52 //=================================================
53 memory mem = new();
54
55 endinterface
56 //+++++++++++++++++++++++++++++++++++++++++++++++++
57 // DUT With interface
58 //+++++++++++++++++++++++++++++++++++++++++++++++++
59 module simple_if (mem_if mif);
60 // Memory array
61 logic [7:0] mem [0:255];
62
63 //=================================================
64 // Read logic
65 //=================================================
66 always @ (posedge mif.clk)
67 if (mif.reset) mif.datao <= 0;
68 else if (mif.ce && ! mif.we) mif.datao <= mem[mif.addr];
69
70 //=================================================
71 // Write Logic
72 //=================================================
73 always @ (posedge mif.clk)
74 if (mif.ce && mif.we) mem[mif.addr] <= mif.datai;
75
76 endmodule
77
78 //+++++++++++++++++++++++++++++++++++++++++++++++++
79 // Testbench
80 //+++++++++++++++++++++++++++++++++++++++++++++++++
81 module coverage_coverpoint();
82
83 logic clk = 0;
84 always #10 clk++;
85 //=================================================
86 // Instianciate Interface and DUT
87 //=================================================
88 mem_if miff(clk);
89 simple_if U_dut(miff);
90 //=================================================
91 // Default clocking
92 //=================================================
93 default clocking dclk @ (posedge clk);
94
95 endclocking
96 //=================================================
97 // Test Vector generation
98 //=================================================
99 initial begin
100 miff.tb.cb.reset <= 1;
101 miff.tb.cb.ce <= 1'b0;
102 miff.tb.cb.we <= 1'b0;
103 miff.tb.cb.addr <= 0;
104 miff.tb.cb.datai <= 0;
105 ##1 miff.tb.cb.reset <= 0;
106 for (int i = 0; i < 3; i ++ ) begin
107 ##1 miff.tb.cb.ce <= 1'b1;
108 miff.tb.cb.we <= 1'b1;
109 miff.tb.cb.addr <= i;
110 miff.tb.cb.datai <= $random;
111 ##3 miff.tb.cb.ce <= 1'b0;
112 $display ("@%0dns Write access address %x, data %x",
113 $time,miff.addr,miff.datai);
114 end
115 for (int i = 0; i < 3; i ++ ) begin
116 ##1 miff.tb.cb.ce <= 1'b1;
117 miff.tb.cb.we <= 1'b0;
118 miff.tb.cb.addr <= i;
119 ##3 miff.tb.cb.ce <= 1'b0;
120 $display ("@%0dns Read access address %x, data %x",
121 $time,miff.addr,miff.datao);
122 end
123 #10 $finish;
124 end
125
126 endmodule
You could download file coverage_points.sv here
|
| |
|
|
| |
|
Simulation : Coverage Points
|
| |
|
|
|
|
|
| |
|
|
| |
|
Generic CoverageGroup
|
| |
|
|
| |
|
|
| |
|
|
|
|
|
| |
|
|
| |
|
Example : Generic CoverageGroup
|
| |
|
|
|
|
You could download file generic_coverage.sv here
|
| |
|
|
| |
|
Simulation : Generic CoverageGroup
|
| |
|
|
|
|
|
| |
|
|
| |
|
Bins transitions
|
| |
|
|
| |
|
|
| |
|
|
| |
|
Example : Bins Transitions
|
| |
|
|
|
|
You could download file bin_transition.sv here
|
| |
|
|
| |
|
Simulation : Bins Transitions
|
| |
|
|
|
|
|
| |
|
|
| |
|
|
| |
|
|
|
|
|
| |
|
|
