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1 module d_ff_gates(d,clk,q,q_bar);
2 input d,clk;
3 output q, q_bar;
4
5 wire n1,n2,n3,q_bar_n;
6 wire cn,dn,n4,n5,n6;
7
8 // First Latch
9 not (n1,d);
10
11 nand (n2,d,clk);
12 nand (n3,n1,clk);
13
14 nand (dn,q_bar_n,n2);
15 nand (q_bar_n,dn,n3);
16
17 // Second Latch
18 not (cn,clk);
19
20 not (n4,dn);
21
22 nand (n5,dn,cn);
23 nand (n6,n4,cn);
24
25 nand (q,q_bar,n5);
26 nand (q_bar,q,n6);
27
28
29 endmodule
You could download file d_ff_gates.v here
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