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Verilog Round Robin Arbiter Model
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1 //----------------------------------------------------
2 // A four level, round-robin arbiter. This was
3 // orginally coded by WD Peterson in VHDL.
4 //----------------------------------------------------
5 module arbiter (
6 clk,
7 rst,
8 req3,
9 req2,
10 req1,
11 req0,
12 gnt3,
13 gnt2,
14 gnt1,
15 gnt0
16 );
17 // --------------Port Declaration-----------------------
18 input clk;
19 input rst;
20 input req3;
21 input req2;
22 input req1;
23 input req0;
24 output gnt3;
25 output gnt2;
26 output gnt1;
27 output gnt0;
28
29 //--------------Internal Registers----------------------
30 wire [1:0] gnt ;
31 wire comreq ;
32 wire beg ;
33 wire [1:0] lgnt ;
34 wire lcomreq ;
35 reg lgnt0 ;
36 reg lgnt1 ;
37 reg lgnt2 ;
38 reg lgnt3 ;
39 reg lasmask ;
40 reg lmask0 ;
41 reg lmask1 ;
42 reg ledge ;
43
44 //--------------Code Starts Here-----------------------
45 always @ (posedge clk)
46 if (rst) begin
47 lgnt0 <= 0;
48 lgnt1 <= 0;
49 lgnt2 <= 0;
50 lgnt3 <= 0;
51 end else begin
52 lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
53 | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
54 | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
55 | (~lcomreq & lmask1 & lmask0 & req0 )
56 | ( lcomreq & lgnt0 );
57 lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
58 | (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
59 | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
60 | (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
61 | ( lcomreq & lgnt1);
62 lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
63 | (~lcomreq & ~lmask1 & lmask0 & req2)
64 | (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
65 | (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
66 | ( lcomreq & lgnt2);
67 lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
68 | (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
69 | (~lcomreq & lmask1 & ~lmask0 & req3)
70 | (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
71 | ( lcomreq & lgnt3);
72 end
73
74 //----------------------------------------------------
75 // lasmask state machine.
76 //----------------------------------------------------
77 assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
78 always @ (posedge clk)
79 begin
80 lasmask <= (beg & ~ledge & ~lasmask);
81 ledge <= (beg & ~ledge & lasmask)
82 | (beg & ledge & ~lasmask);
83 end
84
85 //----------------------------------------------------
86 // comreq logic.
87 //----------------------------------------------------
88 assign lcomreq = ( req3 & lgnt3 )
89 | ( req2 & lgnt2 )
90 | ( req1 & lgnt1 )
91 | ( req0 & lgnt0 );
92
93 //----------------------------------------------------
94 // Encoder logic.
95 //----------------------------------------------------
96 assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
97
98 //----------------------------------------------------
99 // lmask register.
100 //----------------------------------------------------
101 always @ (posedge clk )
102 if( rst ) begin
103 lmask1 <= 0;
104 lmask0 <= 0;
105 end else if(lasmask) begin
106 lmask1 <= lgnt[1];
107 lmask0 <= lgnt[0];
108 end else begin
109 lmask1 <= lmask1;
110 lmask0 <= lmask0;
111 end
112
113 assign comreq = lcomreq;
114 assign gnt = lgnt;
115 //----------------------------------------------------
116 // Drive the outputs
117 //----------------------------------------------------
118 assign gnt3 = lgnt3;
119 assign gnt2 = lgnt2;
120 assign gnt1 = lgnt1;
121 assign gnt0 = lgnt0;
122
123 endmodule
You could download file arbiter.v here
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Testbench Code |
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1 `include "arbiter.v"
2 module top ();
3
4 reg clk;
5 reg rst;
6 reg req3;
7 reg req2;
8 reg req1;
9 reg req0;
10 wire gnt3;
11 wire gnt2;
12 wire gnt1;
13 wire gnt0;
14
15 // Clock generator
16 always #1 clk = ~clk;
17
18 initial begin
19 $dumpfile ("arbiter.vcd");
20 $dumpvars();
21 clk = 0;
22 rst = 1;
23 req0 = 0;
24 req1 = 0;
25 req2 = 0;
26 req3 = 0;
27 #10 rst = 0;
28 repeat (1) @ (posedge clk);
29 req0 <= 1;
30 repeat (1) @ (posedge clk);
31 req0 <= 0;
32 repeat (1) @ (posedge clk);
33 req0 <= 1;
34 req1 <= 1;
35 repeat (1) @ (posedge clk);
36 req2 <= 1;
37 req1 <= 0;
38 repeat (1) @ (posedge clk);
39 req3 <= 1;
40 req2 <= 0;
41 repeat (1) @ (posedge clk);
42 req3 <= 0;
43 repeat (1) @ (posedge clk);
44 req0 <= 0;
45 repeat (1) @ (posedge clk);
46 #10 $finish;
47 end
48
49 // Connect the DUT
50 arbiter U (
51 clk,
52 rst,
53 req3,
54 req2,
55 req1,
56 req0,
57 gnt3,
58 gnt2,
59 gnt1,
60 gnt0
61 );
62
63 endmodule
You could download file arbiter_tb.v here
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Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
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Do you have any Comment? mail me at:deepak@asic-world.com
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