1 <'
  2 struct fifo_sb {
  3     ! fifo : list of byte;
  4 
  5    addItem(data : byte) is {
  6      if (fifo.size() == 7) {
  7        outf("%dns : ERROR : Over flow detected, current occupancy %d\n",
  8          sys.time, fifo.size());
  9      } else {
 10        fifo.push(data);
 11      };
 12    };
 13 
 14    compareItem (data : byte) is {
 15      var cdata : byte = 0;
 16      if (fifo.size() == 0) {
 17        outf("%dns : ERROR : Under flow detected\n", sys.time);
 18      } else {
 19        cdata = fifo.pop0();
 20        if (data  ! = cdata) {
 21          outf("%dns : ERROR : Data mismatch, Expected %x Got %x\n", 
 22            sys.time, cdata, data );
 23        };
 24      };
 25    };
 26 };
 27 '>

   1 <'
   2 struct fifo_driver {
   3   sb : fifo_sb;
   4 
   5   rd_wt     : uint [0..100];
   6   rd_nop_wt : uint [0..100];
   7   wr_wt     : uint [0..100];
   8   wr_nop_wt : uint [0..100];
   9 
  10   keep soft wr_wt == 50;
  11   keep soft rd_wt == 100;
  12   keep soft wr_nop_wt == 100;
  13   keep soft rd_nop_wt == 50;
  14 
  15   rd        : bit;
  16   wr        : bit;
  17 
  18   rd_cmds    : uint;
  19     keep rd_cmds == 100;
  20   wr_cmds    : uint;
  21     keep wr_cmds == 100;
  22 
  23    ! rdDone : bool;
  24    ! wrDone : bool;
  25   
  26   monitorPush()@sys.clk is {
  27     var data : byte = 0;
  28     while (TRUE) {
  29       wait cycle;
  30       if ('top.wr_cs' == 1 &&  'top.wr_en' == 1) {
  31         data = 'top.data_in';
  32         sb.addItem(data);
  33         outf("%dns : Write posting to scoreboard data = %x\n",sys.time, data);
  34       };
  35     };
  36   };
  37 
  38   monitorPop()@sys.clk is {
  39     var data  : byte = 0;
  40     while (TRUE) {
  41       wait cycle;
  42       if ('top.rd_cs' == 1 &&  'top.rd_en' == 1) {
  43         data = 'top.data_out';
  44         sb.compareItem(data);
  45         outf("%dns : Read posting to scoreboard data = %x\n",sys.time, data);
  46       };
  47     };
  48   };
  49 
  50   go()@sys.clk is {
  51     // Assert reset first
  52     reset();
  53     // Start the monitors
  54     wait [5]*cycle;
  55     outf("%dns : Starting Pop and Push monitors\n",sys.time);
  56     start monitorPop();
  57     start monitorPush();
  58     outf("%dns : Starting Pop and Push generators\n",sys.time);
  59     start genPush();
  60     start genPop();
  61 
  62     while ( ! rdDone &&  ! wrDone) {
  63       wait cycle;
  64     };
  65     wait [10]*cycle;
  66     outf("%dns : Terminating simulations\n",sys.time);
  67     stop_run();
  68   };
  69 
  70   reset()@sys.clk is {
  71     wait [5]*cycle;
  72     outf("%dns : Asserting reset\n",sys.time);
  73     'top.rst' = 1'b1;
  74     // Init all variables
  75     rdDone = FALSE;
  76     wrDone = FALSE;
  77     wait [5]*cycle;
  78     'top.rst' = 1'b0;
  79     outf("%dns : Done asserting reset\n",sys.time);
  80   };
  81 
  82   genPush()@sys.clk is {
  83     var data : byte = 0;
  84     for {var i : uint = 0; i < wr_cmds; i = i + 1} do {
  85        gen wr keeping {
  86          soft it == select {
  87            wr_wt     : 1;
  88            wr_nop_wt : 0;
  89          };
  90        };
  91        gen data;
  92        wait cycle;
  93        while ('top.full' == 1'b1) {
  94         'top.wr_cs'   = 1'b0;
  95         'top.wr_en'   = 1'b0;
  96         'top.data_in' = 8'b0;
  97         wait cycle; 
  98        };
  99        if (wr == 1) {
 100          'top.wr_cs'   = 1'b1;
 101          'top.wr_en'   = 1'b1;
 102          'top.data_in' = data;
 103        } else {
 104          'top.wr_cs'   = 1'b0;
 105          'top.wr_en'   = 1'b0;
 106          'top.data_in' = 8'b0;
 107        };
 108     };
 109     wait cycle;
 110     'top.wr_cs'   = 1'b0;
 111     'top.wr_en'   = 1'b0;
 112     'top.data_in' = 8'b0;
 113     wait [10]*cycle;
 114     wrDone = TRUE;
 115   };
 116   
 117   genPop()@sys.clk is {
 118     for {var i : uint = 0; i < rd_cmds; i = i + 1} do {
 119        gen rd keeping {
 120          soft it == select {
 121            rd_wt     : 1;
 122            rd_nop_wt : 0;
 123          };
 124        };
 125        wait cycle;
 126        while ('top.empty' == 1'b1) {
 127         'top.rd_cs'   = 1'b0;
 128         'top.rd_en'   = 1'b0;
 129         wait cycle; 
 130        };
 131        if (rd == 1) {
 132          'top.rd_cs'   = 1'b1;
 133          'top.rd_en'   = 1'b1;
 134        } else {
 135          'top.rd_cs'   = 1'b0;
 136          'top.rd_en'   = 1'b0;
 137        };
 138     };
 139     wait cycle;
 140     'top.rd_cs'   = 1'b0;
 141     'top.rd_en'   = 1'b0;
 142     wait [10]*cycle;
 143     rdDone = TRUE;
 144   };
 145 };
 146 '>

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Deepak Kumar Tala - All rights reserved

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