This module divides the input clock frequency by 3

  1 -------------------------------------------------------
  2 -- Design Name : divide_by_3 
  3 -- File Name   : divide_by_3.vhd
  4 -- Function    : Divide By 3
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11 
 12 entity divide_by_3 is
 13     port (
 14         cout   :out std_logic; -- Output clock
 15         clk    :in  std_logic; -- Input clock
 16         reset  :in  std_logic  -- Input reset
 17     );
 18 end entity;
 19 
 20 architecture rtl of divide_by_3 is
 21     signal pos_cnt :std_logic_vector (1 downto 0);
 22     signal neg_cnt :std_logic_vector (1 downto 0);
 23 begin
 24     process (clk, reset) begin
 25         if (reset = '1') then
 26             pos_cnt <= (others=>'0');
 27         elsif (rising_edge(clk)) then
 28             if (pos_cnt = 2) then
 29                 pos_cnt <= pos_cnt + 1;
 30             end if;
 31         end if;
 32     end process;
 33     
 34     process (clk, reset) begin
 35         if (reset = '1') then
 36             neg_cnt <= (others=>'0');
 37         elsif (falling_edge(clk)) then
 38             if (neg_cnt = 2) then
 39                 neg_cnt <= neg_cnt + 1;
 40             end if;
 41         end if;
 42     end process;
 43     
 44     cout <= '1' when ((pos_cnt /= 2) and (neg_cnt /= 2)) else
 45             '0';
 46 end architecture;
 47 -------------------------------------------------------
 48 --  Testbench to check the divide_by_3 logic
 49 -------------------------------------------------------
 50 library ieee;
 51     use ieee.std_logic_1164.all;
 52     use ieee.std_logic_textio.all;
 53     use std.textio.all;
 54 
 55 entity div3_tb is
 56 end entity;
 57 architecture test of div3_tb is
 58 
 59     signal cout   :std_logic;
 60     signal clk    :std_logic := '1';
 61     signal reset  :std_logic := '1';
 62     
 63     component divide_by_3 is
 64     port (
 65         cout   :out std_logic;
 66         clk    :in  std_logic;
 67         reset  :in  std_logic
 68     );
 69     end component;
 70 begin
 71 
 72    -- Generate clock
 73     clk   <= not clk after 10 ns;
 74     reset <= '0' after 20 ns;
 75 
 76     Inst_div3 : divide_by_3
 77     port map (
 78         cout   => cout,  -- Output
 79         clk    => clk,   -- Input
 80         reset  => reset  -- Iinput
 81     );
 82 end architecture;

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