1 -------------------------------------------------------
  2 -- Design Name : clk_div_45
  3 -- File Name   : clk_div_45.vhd
  4 -- Function    : Divide by 4.5
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11 
 12 entity clk_div_45 is
 13     port (
 14         cout   :out std_logic; -- Output clock
 15         enable :in  std_logic; -- Enable counting
 16         clk    :in  std_logic; -- Input clock
 17         reset  :in  std_logic  -- Input reset
 18     );
 19 end entity;
 20 
 21 architecture rtl of clk_div_45 is
 22     signal counter1 :std_logic_vector (2 downto 0);
 23     signal counter2 :std_logic_vector (2 downto 0);
 24     signal toggle1  :std_logic;
 25     signal toggle2  :std_logic;
 26 
 27 begin
 28     process (clk) begin
 29         if (rising_edge(clk)) then
 30             if (enable = '0') then
 31                 counter1 <= (others=>'0');
 32                 toggle1  <= '0';
 33             elsif ((counter1 = 3 and toggle2 = '1') or
 34                    (toggle1 = '0' and counter1 = 4)) then
 35                 counter1 <= (others=>'0');
 36                 toggle1  <= not toggle1;
 37             else
 38                 counter1 <= counter1 + 1;
 39             end if;
 40         end if;
 41     end process;
 42 
 43     process (clk) begin
 44         if (falling_edge(clk)) then
 45             if (enable = '0') then
 46                 counter2 <= (others=>'0');
 47                 toggle2  <= '0';
 48             elsif ((counter2 = 3 and toggle2 = '0') or
 49                    (toggle2 = '1' and counter2 = 4)) then
 50                 counter2 <= (others=>'0');
 51                 toggle2  <= not toggle2;
 52             else
 53                 counter2 <= counter2 + 1;
 54             end if;
 55         end if;
 56     end process;
 57     cout <= enable when (counter1 < 3 and counter2 < 3) else
 58             '0';
 59 end architecture;

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