1 -------------------------------------------------------
  2 -- Design Name : clk_div
  3 -- File Name   : clk_div.vhd
  4 -- Function    : Divide by two counter
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity clk_div is
 12     port (
 13         cout   :out std_logic; -- Output clock
 14         enable :in  std_logic; -- Enable counting
 15         clk    :in  std_logic; -- Input clock
 16         reset  :in  std_logic  -- Input reset
 17     );
 18 end entity;
 19 
 20 architecture rtl of clk_div is
 21     signal clk_div :std_logic;
 22 begin
 23     process (clk, reset) begin
 24         if (reset = '1') then
 25             clk_div <= '0';
 26         elsif (rising_edge(clk)) then
 27             if (enable = '1') then
 28                 clk_div <= not clk_div;
 29             end if;
 30         end if;
 31     end process;
 32     cout <= clk_div;
 33 end architecture;

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