1 -------------------------------------------------------
  2 -- Design Name : one_hot_cnt
  3 -- File Name   : one_hot_cnt.vhd
  4 -- Function    : 8 bit one hot counter
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity one_hot_cnt is
 12     port (
 13         cout   :out std_logic_vector (7 downto 0); -- Output of the counter
 14         enable :in  std_logic;                     -- Enable counting
 15         clk    :in  std_logic;                     -- Input clock
 16         reset  :in  std_logic                      -- Input reset
 17     );
 18 end entity;
 19 
 20 architecture rtl of one_hot_cnt is 
 21     signal count :std_logic_vector (7 downto 0); 
 22 begin 
 23     process (clk) begin
 24         if (rising_edge(clk)) then 
 25             if (reset = '1') then 
 26                 count <= "00000001"; 
 27             elsif (enable = '1') then 
 28                 count <= (count(6) & count(5) & count(4) & count(3) & 
 29                           count(2) & count(1) & count(0) & count(7)); 
 30             end if;
 31         end if;
 32     end process;
 33     cout <= count;
 34 end architecture;

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