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  ../images/main/bullet_green_ball.gif Introduction

In today's ASIC world, we have gate count increasing every day, thus the challenge to verify them. In the past the verification was done with languages which were meant for designing. Like the Hardware description language (HDL's) Verilog does not provide the capability to verify complex designs. Thus there was limitation on how best you could verify the design. To fill this gap, Hardware Verification Languages (HVL's) like "e", "VERA", "TestBuilder C++" were developed.

   

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VERA is basically the Language/tool/compiler/debugger to help write testbench to verify HDL. VERA language is used for basically describe testbench, which has the capability to generate random test vectors, ability to interface with HDL's, provides means to do functional coverage, scoreboards.

   

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I started learn VERA in year 2001, it was easy to learn, but as time passed it became clear that in long run, hardware Verification Languages (HVL's) like E and VERA are going to dominate the pre-silicon verification. Here in next few pages, I will share what I have learnt all these years with VERA and how the typical testbench with HVL's looks like.

   

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If you want to know how fast you can pick up VERA language. Well if you know C++ or any other Object Oriented Language then VERA language, then it should not take more than one week.

   

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As usual, I would like to hear from you if you have a suggestion or you see any problem in approach or mistakes in my examples

   

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Copyright 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com