HDL tasks can be called from Vera, and vice versa. This enables the reuse of tasks and functions. Personally I found forcing and releasing of hdl signals in DUT done with HDL tasks fun to do.

We will be looking at the following.

• HDL Task called from Vera
• Vera Task called from HDL

To declare an HDL task in OpenVera, use this syntax within your main program module:

Syntax

hdl_task task_name (argument_list) "inst_path";

Where

• task_name : Is the name of the HDL task you want to call.
• argument_list : Are passed from OpenVera to the HDL when the task is called. Arguments can be of type integer or bit vector.
• inst_path : Is the instantiation path of the task in the HDL. It identifies the HDL task within the HDL hierarchy starting at the top level HDL module.

Note : For inout in HDL task/function, use ref to access it.

  1 #include "vera_defines.vrh"
  2 
  3 hdl_task doAccess (bit [7:0] addr,bit rw, var bit [7:0] data) "top.do_rw";
  4 
  5 // Top level program 
  6 program hdl2vera {
  7    bit [7:0] data = 0;
  8    bit [7:0] addr = 0;
  9    bit       rw   = 0;
 10    integer i;
 11    // Access with port.$<sig name>
 12    for (i=0; i < 10; i++) {
 13      @ (posedge CLOCK);
 14      addr = i;
 15      data = random();
 16      doAccess(addr,1,data);
 17    }
 18    // Access with interface.<sig name>
 19    for (i=0; i < 10; i++) {
 20      @ (posedge CLOCK);
 21      addr = i;
 22      doAccess(addr,0,data);
 23      printf("--Vera : Address %x data %x--\n",addr,data);
 24    }
 25 }

Verilog

  1 module top ();
  2 // Internal variables
  3 reg        clk;
  4 reg [7:0]  mem [0:255];
  5 wire [7:0] rdata;     
  6 
  7 reg  [7:0] addr;     
  8 reg  [7:0] wdata;     
  9 reg        wr,rd;
 10 
 11 assign rdata = (rd) ? mem[addr] : 8'b0;
 12 
 13 always @ (addr or wr or wdata)
 14   if (wr) mem[addr] = wdata;
 15 
 16 // Connect the program here
 17 hdl2vera vshell(
 18  .SystemClock (clk)
 19 );
 20 // Init all the variables
 21 initial begin
 22   clk = 0;
 23 end
 24 // Clock generator
 25 always #1 clk = ~clk;
 26 
 27 task do_rw;
 28   input [7:0] taddr;
 29   input       trw;
 30   inout [7:0] tdata;
 31   begin
 32     if (~trw) begin
 33       @ (posedge clk);
 34       addr = taddr;
 35       rd = 1;
 36       wr = 0;
 37       @ (posedge clk);
 38       $display("%0dns Reading from address %x, data %x",$time,taddr, rdata);
 39       tdata = rdata;
 40       rd = 0;
 41       addr = 0;
 42     end else begin
 43       @ (posedge clk);
 44       $display("%0dns Wriing to address %x with data %x",$time,taddr,tdata);
 45       addr = taddr;
 46       rd = 0;
 47       wr = 1;
 48       wdata = tdata;
 49       @ (posedge clk);
 50       wr = 0;
 51       addr = 0;
 52     end
 53   end
 54 endtask
 55 
 56 endmodule

 3ns Wriing to address 00 with data ac
 7ns Wriing to address 01 with data 1d
 11ns Wriing to address 02 with data bf
 15ns Wriing to address 03 with data c9
 19ns Wriing to address 04 with data 5d
 23ns Wriing to address 05 with data 6a
 27ns Wriing to address 06 with data 46
 31ns Wriing to address 07 with data 43
 35ns Wriing to address 08 with data 5f
 39ns Wriing to address 09 with data 15
 45ns Reading from address 00, data ac
 --Vera : Address 00 data ac--
 49ns Reading from address 01, data 1d
 --Vera : Address 01 data 1d--
 53ns Reading from address 02, data bf
 --Vera : Address 02 data bf--
 57ns Reading from address 03, data c9
 --Vera : Address 03 data c9--
 61ns Reading from address 04, data 5d
 --Vera : Address 04 data 5d--
 65ns Reading from address 05, data 6a
 --Vera : Address 05 data 6a--
 69ns Reading from address 06, data 46
 --Vera : Address 06 data 46--
 73ns Reading from address 07, data 43
 --Vera : Address 07 data 43--
 77ns Reading from address 08, data 5f
 --Vera : Address 08 data 5f--
 81ns Reading from address 09, data 15
 --Vera : Address 09 data 15--

If you want to call Vera tasks from an HDL design, the tasks must be declared with the export construct in the top level Vera file (the program file). Exported tasks behave as normal Vera tasks and can be called within the Vera code. Vera imposes no restrictions on the contents of exported tasks. Exported tasks can have delays, forks/joins, and calls to other tasks or functions including calls back to HDL tasks.

Syntax

export task task_name (argument_list)
{
  task_contents;
}

Where

• argument_list : The arguments are passed from the HDL to Vera when the task is called. They can be of type integer, reg, bit vector or string. The integer, reg, bit vector arguments can be var and non-var variables. var string, however, is not supported.
• task_contents : can be any OpenVera code valid in normal task definitions.

Calling Exported Vera Tasks : When you declare an export task, a task with the same name is generated in the vera_shell module. It is called from the HDL as vshell.task_name.

  1 #include "vera_defines.vrh"
  2 
  3 export task  printData (bit [7:0] data) {
  4   printf("%0dns Data = %0x\n",get_time(LO),data);
  5 }
  6 
  7 export task setDone(bit doneValue) {
  8  done = doneValue;
  9 }
 10 // Top level program 
 11 program vera2hdl {
 12   bit done = 0;
 13   while (done == 0) {
 14    @ (posedge CLOCK);
 15   }
 16 }
 17 
 18 

Verilog

  1 module top ();
  2 // Internal variables
  3 reg        clk;
  4 
  5 // Connect the program here
  6 vera2hdl vshell(
  7  .SystemClock (clk)
  8 );
  9 // Init all the variables
 10 initial begin
 11   clk = 0;
 12 end
 13 // Clock generator
 14 always #1 clk = ~clk;
 15 
 16 
 17 initial begin
 18   repeat (10) #10 vshell.printData($random);
 19   repeat(10) @ (posedge clk);
 20   vshell.setDone(1);
 21 end
 22 
 23 endmodule

 10ns Data = 24
 20ns Data = 81
 30ns Data = 9
 40ns Data = 63
 50ns Data = d
 60ns Data = 8d
 70ns Data = 65
 80ns Data = 12
 90ns Data = 1
 100ns Data = d

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Deepak Kumar Tala - All rights reserved

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