Signals can be referenced directly through following two ways. There is no other method other then this.

• the port variable
• the interface

Syntax

port_variable.$signal_name
interface.signal_name

Where

• port_variable : Is the name of the port variable that has established connections.
• interface : Is the name of a Vera interface.

  1 #include "vera_defines.vrh"
  2 
  3 // Port Declaration
  4 port mem_p {
  5   clock;
  6   addr;
  7   wr;
  8   rd;
  9   rdata;
 10   wdata;
 11 }
 12 
 13 // This is what connects with HDL
 14 interface mem_if {
 15  input  clock CLOCK;
 16  output [7:0] addr PHOLD #1;
 17  input [7:0]  rdata PSAMPLE #-1;
 18  output [7:0] wdata PHOLD #1;
 19  output       wr PHOLD #1;
 20  output       rd PHOLD #1;
 21 }
 22 
 23 // Now bind interface with Port
 24 bind mem_p mem_bind {
 25   clock  mem_if.clock;
 26   addr   mem_if.addr;
 27   wr     mem_if.wr;
 28   rd     mem_if.rd;
 29   rdata  mem_if.rdata; 
 30   wdata  mem_if.wdata;
 31 }
 32 // Top level program 
 33 program sig_ref {
 34    mem_p mem = mem_bind;
 35    bit [7:0] data = 0;
 36    integer i;
 37    mem.$wr = 0; // port.$signal
 38    mem_if.rd = 0; // interface.signal
 39    // Access with port.$<sig name>
 40    for (i=0; i < 10; i++) {
 41      @ (posedge mem.$clock);
 42      mem.$addr = i;
 43      data = random();
 44      mem.$wdata = data;
 45      mem.$wr = 1;
 46      printf("Writing address %0x, with data %0x\n",i,data);
 47      @ (posedge mem.$clock);
 48      mem.$wr = 0;
 49    }
 50    // Access with interface.<sig name>
 51    for (i=0; i < 10; i++) {
 52      @ (posedge mem_if.clock);
 53      mem_if.addr = i;
 54      mem_if.rd = 1;
 55      printf("Reading address %0x",i);
 56      @ (posedge mem_if.clock);
 57      printf(", data %0x\n",mem_if.rdata);
 58      mem_if.rd = 0;
 59 
 60    }
 61 }

Verilog

  1 module sig_ref_verilog ();
  2 // Internal variables
  3 reg        clk;
  4 reg [7:0]  mem [0:255];
  5 wire [7:0] rdata;     
  6 
  7 wire [7:0] addr;     
  8 wire [7:0] wdata;     
  9 wire       wr,rd;
 10 
 11 assign rdata = (rd) ? mem[addr] : 8'b0;
 12 
 13 always @ (addr or wr or wdata)
 14   if (wr) mem[addr] = wdata;
 15 
 16 // Connect the program here
 17 sig_ref vshell(
 18  .SystemClock (clk),
 19  .\mem_if.clock       (clk),
 20  .\mem_if.addr        (addr),
 21  .\mem_if.rdata       (rdata),
 22  .\mem_if.wdata       (wdata),
 23  .\mem_if.wr          (wr),
 24  .\mem_if.rd          (rd)
 25 );
 26 // Init all the variables
 27 initial begin
 28   clk = 0;
 29 end
 30 // Clock generator
 31 always  #1  clk = ~clk;
 32 
 33 endmodule

 Writing address 0, with data ac
 Writing address 1, with data 1d
 Writing address 2, with data bf
 Writing address 3, with data c9
 Writing address 4, with data 5d
 Writing address 5, with data 6a
 Writing address 6, with data 46
 Writing address 7, with data 43
 Writing address 8, with data 5f
 Writing address 9, with data 15
 Reading address 0, data ac
 Reading address 1, data 1d
 Reading address 2, data bf
 Reading address 3, data c9
 Reading address 4, data 5d
 Reading address 5, data 6a
 Reading address 6, data 46
 Reading address 7, data 43
 Reading address 8, data 5f
 Reading address 9, data 15

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

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