Connecting the interface signals from Vera to HDL can be done in three ways.

• Vera Shell
• Direct HDL node connection
• signal_connect()

First two methods are static connections and signal_connect() method is dynamic connection. First two offer far better simulation performance compared to signal_connect().

Vera shell file generated after compilation of file containing Vera Program. This shell file is verilog file for verilog simulations, and this file contains the port declarations that map to the interface declaration in Vera testbench. This vera shell contains the additional input SystemClock. Simulator specific PLI calls are included in this shell. Example in interface section shows how to connect a Vera shell to Verilog. Below is code section where shell is connected to Verilog.

  1 // This is how a vera shell is connected
  2 interface_ex vshell(
  3  .SystemClock            (clk),
  4  .\sample_if.clock       (clk),
  5  .\sample_if.reset       (rst),
  6  .\sample_if.enable      (counter_en),
  7  .\sample_if.cout        (counter),
  8  .\sample_if.data        (data),
  9  .\sample_if.ddr_data_in (ddr_data_in)
 10 );

A Vera interface signal can be connected to any user-specified HDL signal in a design using the hdl_node option. Such connections are a convenient way to monitor and drive internal DUT signals. When the hdl_node option is used, the interface signal is omitted from the shell´s port list. When the option is not used, a port will be added to the shell module for the signal.

  1 #include "vera_defines.vrh"
  2 
  3 interface hdl_node_if {
  4  // Other signals are sampled with respect to this
  5  input clock          CLOCK      hdl_node "hdl_node_verilog.clk"; 
  6  output reset         PHOLD#1    hdl_node "hdl_node_verilog.rst";
  7  output enable        PHOLD#1    hdl_node "hdl_node_verilog.counter_en";
  8  input [7:0] cout     PSAMPLE#-1 hdl_node "hdl_node_verilog.counter";
  9 }
 10 
 11 program hdl_node_ex {
 12      // Start the actual test here
 13    @ (posedge hdl_node_if.clock);
 14    printf("Asserting Reset\n");
 15    hdl_node_if.reset = 1;
 16    hdl_node_if.enable = 0;
 17    @ (posedge hdl_node_if.clock);
 18    printf("Deasserting Reset\n");
 19    hdl_node_if.reset = 0;
 20    @ (posedge hdl_node_if.clock);
 21    printf("Asserting Enable\n");
 22    hdl_node_if.enable = 1;
 23    repeat(10) {
 24      @ (posedge hdl_node_if.clock);
 25      printf("Counter value %x\n",hdl_node_if.cout);
 26    }
 27    @ (posedge hdl_node_if.clock);
 28    printf("Deasserting Enable\n");
 29    hdl_node_if.enable = 0;
 30 }

Verilog

  1 module hdl_node_verilog ();
  2 // Internal variables
  3 reg [3:0] counter;
  4 reg       clk;
  5 wire      rst;
  6 wire      counter_en;
  7 
  8 
  9 // Connect the program here
 10 hdl_node_ex vshell(
 11  .SystemClock            (clk)
 12 );
 13 // Init all the variables
 14 initial begin
 15   clk = 0;
 16 end
 17 // Clock generator
 18 always  #1  clk = ~clk;
 19 // Counter code
 20 always @ (posedge clk)
 21   if (rst) counter <= 0;
 22   else if (counter_en) counter <= counter + 1;
 23 
 24 endmodule

 Asserting Reset
 Deasserting Reset
 Asserting Enable
 Counter value 00
 Counter value 01
 Counter value 02
 Counter value 03
 Counter value 04
 Counter value 05
 Counter value 06
 Counter value 07
 Counter value 08
 Counter value 09
 Deasserting Enable

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Deepak Kumar Tala - All rights reserved

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