Vera signals, also referred to as interface signals, connect Vera to internal nodes and ports of the DUT. Driving and sampling Vera signals within the Vera testbench drives and samples the corresponding nodes in the DUT.

Timing for sampling and driving the Vera signals is relative to the interface's clock; consequently, grouping the Vera signals within an interface allows signals to be driven or sampled within the Vera program without having to explicitly call a clock, or having to specify timing.

We will be covering following topics in detail.

• Vera Interfaces
• Interface Signal Connection
• Virtual Port Signal Connection
• signal_connect()
• HDL Tasks
• Driving and Sampling

The interface specification is used to group Vera signals by clock domain. Each interface may include, at most, one input signal of type CLOCK. The non-clock signals defined in an interface are sampled and driven on the edges of this clock. If an input signal of type CLOCK is not designated, then the interface signals are synchronized using SystemClock.

Clock domains can be overlapped by connecting an HDL node to signals in different interfaces. For example, an HDL signal is associated with multiple clocks by mapping it in multiple interface specifications. Interfaces are top level constructs and must be declared in the Vera program file. The declarations must be repeated, typically with a #include directive, in any non-program file that uses the interfaces.

Syntax

interface interface_name
{
signal_direction [signal_width] signal_name signal_type
[skew] [depth value][vca q_value][force][hdl_node "hdl_path"];
}

Where

• signal_direction : This can be one of the following
• input : indicates that the signal goes from the DUT to Vera.
• output : output indicates that the signal goes from Vera to the DUT.
• inout : specifies a bi-directional signal.
• signal_width : The signal_width is a range specifying the width of a vector signal. It must be in the form [msb:lsb]. Interface signals can have any integer lsb value, even a negative value. The default width is 1.
• signal_name : The signal_name identifies the signal being defined. It is the Vera name for the HDL signal being connected.
• signal_type : There are many signals types, most commonly used one are
• NHOLD : Used for output, Signal is driven on the negative edge of the interface clock.
• PHOLD : Used for output, Signal is driven on the positive edge of the interface clock.
• PHOLD NHOLD : Output can be driven at both the edges.
• NSAMPLE : Used for input, Signal is sampled (evaluated) at the negative edge of the interface clock.
• PSAMPLE : Used for input, Signal is sampled (evaluated) at the postive edge of the interface clock.
• PSAMPLE NSAMPLE : The input signal can be sampled at both the edges of the interface clock.
• CLOCK : Clock signal to which the other signals in the interface synchronize.
• PSAMPLE PHOLD :Used with inout, The inout signal is sampled and driven on the positive edge of the interface clock.
• NSAMPLE NHOLD :Used with inout, The inout signal is sampled and driven on the negative edge of the interface clock.
• PSAMPLE PHOLD NSAMPLE NHOLD :Used with inout, The inout signal is sampled and driven on both edge's of the interface clock.
• skew : skew must be an integer value. The skew determines how long before the synchronized edge the signal is sampled, or how long after the synchronized edge the signal is driven. The units of skew are expressed in terms of the timescale of the Vera shell.
• depth value : value must be a non-negative integer. The default value is 0. Input signals are typically sampled on the synchronized edge in the current cycle. However, an input signal can be sampled on a previous synchronized edge. To reference such a signal value, the signal depth must be specified in the signal declaration. The value specifies the number of synchronized edges that are stored for back-reference. Depth cannot be specified on an output signal.
• force : In the interface, you must indicate which signals may be forced in a testbench by using the force attribute.
• hdl_node hdl_path : The hdl_path , used in conjunction with the hdl_node keyword, is the HDL path to the specified signal. It must be surrounded by double quotes.

  1 #include "vera_defines.vrh"
  2 
  3 interface sample_if {
  4  // Other signals are sampled with respect to this
  5  input clock          CLOCK; 
  6  output reset         PHOLD#1;
  7  output enable        PHOLD#1;
  8  input [7:0] cout     PSAMPLE #-1;
  9  inout data           PSAMPLE PHOLD NSAMPLE#-1 NHOLD #1;
 10  input ddr_data_in    PSAMPLE NSAMPLE;
 11  input data_in        PSAMPLE #-1 hdl_node "sample_if_verilog.data";
 12  input [7:0] count    PSAMPLE #-1 hdl_node "sample_if_verilog.counter";
 13  output  nenable      PHOLD   #1 hdl_node "sample_if_verilog.counter_en";
 14 }
 15 
 16 program interface_ex {
 17      // Start the actual test here
 18    @ (posedge sample_if.clock);
 19    printf("Asserting Reset\n");
 20    sample_if.reset = 1;
 21    sample_if.enable = 0;
 22    @ (posedge sample_if.clock);
 23    printf("Deasserting Reset\n");
 24    sample_if.reset = 0;
 25    @ (posedge sample_if.clock);
 26    printf("Asserting Enable\n");
 27    sample_if.enable = 1;
 28    repeat(10) {
 29      @ (posedge sample_if.clock);
 30      printf("Counter value %x\n",sample_if.cout);
 31      printf("DDR sample pos %x\n",sample_if.ddr_data_in);
 32      @ (negedge sample_if.clock);
 33      printf("DDR sample neg %x\n",sample_if.ddr_data_in);
 34    }
 35    @ (posedge sample_if.clock);
 36    printf("Deasserting Enable\n");
 37    sample_if.enable = 0;
 38 }

Verilog File

  1 module sample_if_verilog ();
  2 // Internal variables
  3 reg [3:0] counter;
  4 reg       clk;
  5 wire      rst;
  6 wire      counter_en;
  7 wire      data;
  8 wire      ddr_data_in;
  9 wire      ddr_data_out;
 10 
 11 assign data = (counter[2]) ? counter[0] : counter[1];
 12 assign ddr_data_in = (clk) ? counter[0] : counter[1];
 13 
 14 // Connect the program here
 15 interface_ex vshell(
 16  .SystemClock            (clk),
 17  .\sample_if.clock       (clk),
 18  .\sample_if.reset       (rst),
 19  .\sample_if.enable      (counter_en),
 20  .\sample_if.cout        (counter),
 21  .\sample_if.data        (data),
 22  .\sample_if.ddr_data_in (ddr_data_in)
 23 );
 24 // Init all the variables
 25 initial begin
 26   clk = 0;
 27 end
 28 // Clock generator
 29 always  #1  clk = ~clk;
 30 // Counter code
 31 always @ (posedge clk)
 32   if (rst) counter <= 0;
 33   else if (counter_en) counter <= counter + 1;
 34 
 35 endmodule

 Asserting Reset
 Deasserting Reset
 Asserting Enable
 Counter value 00
 DDR sample pos 1
 DDR sample neg 0
 Counter value 01
 DDR sample pos 0
 DDR sample neg 1
 Counter value 02
 DDR sample pos 1
 DDR sample neg 1
 Counter value 03
 DDR sample pos 0
 DDR sample neg 0
 Counter value 04
 DDR sample pos 1
 DDR sample neg 0
 Counter value 05
 DDR sample pos 0
 DDR sample neg 1
 Counter value 06
 DDR sample pos 1
 DDR sample neg 1
 Counter value 07
 DDR sample pos 0
 DDR sample neg 0
 Counter value 08
 DDR sample pos 1
 DDR sample neg 0
 Counter value 09
 DDR sample pos 0
 DDR sample neg 1
 Deasserting Enable

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com