In SystemVerilog $exit is introduced for use in program block. Calling $exit closes all the threads spawned from current program.

$exit is called automatically when execution reaches end of initial block inside a program. Below example shows this.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 // Simple Program with ports
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 program exit_simple(input wire clk,output logic reset,
  5             enable, input logic [3:0] count);
  6   //=================================================
  7   // Initial block inside program block
  8   //=================================================
  9   initial begin
 10     $monitor("@%0dns count = %0d",$time,count);
 11     fork
 12        do_something();
 13     join_none
 14     reset = 1;
 15     enable = 0;
 16      #20  reset = 0;
 17     @ (posedge clk);
 18     enable = 1;
 19     repeat (5) @ (posedge clk);
 20     enable = 0;
 21      #10  $exit();
 22      #100  $display("%0dns Terminating simulation", $time);
 23     $finish;
 24   end
 25   //=================================================
 26   // Simple task
 27   //=================================================
 28   task do_something();
 29     while (1) begin
 30         #5  $display("%0dns inside do_something task", $time);
 31     end
 32   endtask
 33 
 34 endprogram
 35 //=================================================
 36 //  Module which instanciates program block
 37 //=================================================
 38 module exit_program();
 39 logic clk  = 0;
 40 always  #1  clk ++;
 41 logic [3:0] count;
 42 wire reset,enable;
 43 //=================================================
 44 // Simple up counter
 45 //=================================================
 46 always @ (posedge clk)
 47  if (reset) count <= 0;
 48  else if (enable) count ++;
 49 //=================================================
 50 // Program is connected like a module
 51 //=================================================
 52 exit_simple prg_simple(clk,reset,enable,count);
 53 
 54 endmodule

 @0ns count = x
 @1ns count = 0
 5ns inside do_something task
 10ns inside do_something task
 15ns inside do_something task
 20ns inside do_something task
 @23ns count = 1
 25ns inside do_something task
 @25ns count = 2
 @27ns count = 3
 @29ns count = 4
 30ns inside do_something task
 @31ns count = 5
 35ns inside do_something task
 40ns inside do_something task

Copyright © 1998-2025

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com