module in verilog is used for describing hardware, it can contain, always, intial and assign statments. To have clear sepration between testbench and design, SystemVerilog introduces program, which contains full enviroment for testbench.

A Program serves following purpose.

• It provides an entry point to the execution of testbenches.
• It creates a scope that encapsulates programwide data, tasks, and functions.
• It provides a syntactic context that specifies scheduling in the Reactive region.

As such it is better use clocking for driving or sampling signals from outside to avoid race. A program is similar to module, so it can contain ports, interfaces, final and initial statments.

Note : Program block can not contain always block.

One more important limitation of program block is. A module (design) can not call task/function inside a program block. But a program can call task/function inside module (design).

Below is simple program example.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 // Simple Program with ports
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 program simple(input wire clk,output logic reset,
  5             enable, input logic [3:0] count);
  6   //=================================================
  7   // Initial block inside program block
  8   //=================================================
  9   initial begin
 10     $monitor("@%0dns count = %0d",$time,count);
 11     reset = 1;
 12     enable = 0;
 13      #20  reset = 0;
 14     @ (posedge clk);
 15     enable = 1;
 16     repeat (5) @ (posedge clk);
 17     enable = 0;
 18     // Call task in module
 19     simple_program.do_it();
 20   end
 21   //=================================================
 22   // Task inside a module
 23   //=================================================
 24   task do_it();
 25     $display("%m I am inside program");
 26   endtask
 27 
 28 endprogram
 29 //=================================================
 30 //  Module which instanciates program block
 31 //=================================================
 32 module simple_program();
 33 logic clk  = 0;
 34 always  #1  clk ++;
 35 logic [3:0] count;
 36 wire reset,enable;
 37 //=================================================
 38 // Simple up counter
 39 //=================================================
 40 always @ (posedge clk)
 41  if (reset) count <= 0;
 42  else if (enable) count ++;
 43 //=================================================
 44 // Program is connected like a module
 45 //=================================================
 46 simple prg_simple(clk,reset,enable,count);
 47 //=================================================
 48 // Task inside a module
 49 //=================================================
 50 task do_it();
 51   $display("%m I am inside module");
 52 endtask
 53 //=================================================
 54 // Below code is illegal
 55 //=================================================
 56 //initial begin
 57 //  prg_simple.do_it();
 58 //end
 59 
 60 endmodule

 @0ns count = x
 @1ns count = 0
 @23ns count = 1
 @25ns count = 2
 @27ns count = 3
 @29ns count = 4
 simple_program.do_it I am inside module
 @31ns count = 5

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Deepak Kumar Tala - All rights reserved

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