Wires and Variables inside a interface allows communications within a interface, but a interface needs to interface with other interfaces, then ports in interface can be used. Ports can be of any type as in the case of a module.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 // Define the interface
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 interface mem_if (
  5   input  wire         clk,
  6   input  wire         reset,
  7   input  wire         we,
  8   input  wire         ce,
  9   input  wire   [7:0] datai,
 10   output logic  [7:0] datao,
 11   input  wire   [7:0] addr
 12 );
 13 endinterface
 14 
 15 //+++++++++++++++++++++++++++++++++++++++++++++++++
 16 //   DUT With interface
 17 //+++++++++++++++++++++++++++++++++++++++++++++++++
 18 module simple_if (mem_if mif);
 19 // Memory array
 20 logic [7:0] mem [0:255];
 21 //=================================================
 22 // Read logic
 23 //=================================================
 24 always @ (posedge mif.clk)
 25  if (mif.reset) mif.datao <= 0;
 26  else if (mif.ce &&  ! mif.we) begin
 27    mif.datao <= mem[mif.addr];
 28  end
 29 //=================================================
 30 // Write Logic
 31 //=================================================
 32 always @ (posedge mif.clk)
 33  if (mif.ce && mif.we) begin
 34    mem[mif.addr] <= mif.datai;
 35  end
 36 
 37 endmodule
 38 
 39 //+++++++++++++++++++++++++++++++++++++++++++++++++
 40 //  Testbench
 41 //+++++++++++++++++++++++++++++++++++++++++++++++++
 42 module tb();
 43 
 44 logic clk = 0;
 45 always  #10  clk++;
 46 logic   reset,ce,we;
 47 logic [7:0] datai,addr;
 48 wire  [7:0] datao;
 49 //=================================================
 50 // Instianciate Interface and DUT 
 51 //=================================================
 52 mem_if miff(
 53  .clk     (clk),
 54  .reset   (reset),
 55  .ce      (ce),
 56  .we      (we),
 57  .datai   (datai),
 58  .datao   (datao),
 59  .addr    (addr)
 60 );
 61 
 62 simple_if U_dut(.mif (miff));
 63 //=================================================
 64 // Test Vector generation
 65 //=================================================
 66 initial begin
 67   reset <= 1;
 68   ce <= 1'b0;
 69   we <= 1'b0;
 70   addr <= 0;
 71   datai <= 0;
 72   repeat (10) @ (posedge clk);
 73   reset <= 0;
 74   for (int i = 0; i < 3; i ++ ) begin
 75     @ (posedge clk) ce <= 1'b1;
 76     we <= 1'b1;
 77     addr <= i;
 78     datai <= $random;
 79     @ (posedge clk) ce <= 1'b0;
 80     $display ("@%0dns Write access address %x, data %x",
 81       $time,addr, datai);
 82   end
 83   for (int i = 0; i < 3; i ++ ) begin
 84     @ (posedge clk) ce <= 1'b1;
 85     we <= 1'b0;
 86     addr <= i;
 87     repeat (2) @ (posedge clk);
 88     ce <= 1'b0;
 89     $display ("@%0dns Read access address %x, data %x",
 90       $time,addr, datao);
 91   end
 92    #10  $finish;
 93 end
 94 
 95 endmodule

 @230ns Write access address 00, data 24
 @270ns Write access address 01, data 81
 @310ns Write access address 02, data 09
 @370ns Read access address 00, data 24
 @430ns Read access address 01, data 81
 @490ns Read access address 02, data 09

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com