One of the best features of SystemVerilog is =interface. Basically interface feature allows bundling of ports. The interface is instantiated in a design and can be accessed through a port as a single item, and the component nets or variables referenced where needed. A significant proportion of a Verilog design often consists of port lists and port connection lists, which are just repetitions of names. The ability to replace a group of names by a single name can significantly reduce the size of a description and improve its maintainability.

Interfaces can also contain tasks and functions. To facilate master/slave kind of support (input of one is output of other), interface contains modport.

We will be discussing all this in detail in next few pages. But before that lets look at simple example.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 // Define the interface
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 interface mem_if (input wire clk);
  5   wire        reset;
  6   wire        we;
  7   wire        ce;
  8   wire  [7:0] datai;
  9   logic [7:0] datao;
 10   wire  [7:0] addr;
 11   //=================================================
 12   // Clocking block for testbench
 13   //=================================================
 14   clocking cb @ (posedge clk);
 15     output reset, we, ce, datai,addr;
 16     input  datao;
 17   endclocking
 18   //=================================================
 19   // Modport for testbench 
 20   //=================================================
 21   modport  tb (clocking cb, input clk);
 22 
 23 endinterface
 24 
 25 //+++++++++++++++++++++++++++++++++++++++++++++++++
 26 //   DUT With interface
 27 //+++++++++++++++++++++++++++++++++++++++++++++++++
 28 module simple_if (mem_if mif);
 29 // Memory array
 30 logic [7:0] mem [0:255];
 31 
 32 //=================================================
 33 // Read logic
 34 //=================================================
 35 always @ (posedge mif.clk)
 36  if (mif.reset) mif.datao <= 0;
 37  else if (mif.ce &&  ! mif.we) mif.datao <= mem[mif.addr];
 38 
 39 //=================================================
 40 // Write Logic
 41 //=================================================
 42 always @ (posedge mif.clk)
 43  if (mif.ce && mif.we) mem[mif.addr] <= mif.datai;
 44 
 45 endmodule
 46 
 47 //+++++++++++++++++++++++++++++++++++++++++++++++++
 48 //  Testbench
 49 //+++++++++++++++++++++++++++++++++++++++++++++++++
 50 module tb();
 51 
 52 logic clk = 0;
 53 always  #10  clk++;
 54 //=================================================
 55 // Instianciate Interface and DUT 
 56 //=================================================
 57 mem_if miff(clk);
 58 simple_if U_dut(miff);
 59 //=================================================
 60 // Default clocking  
 61 //=================================================
 62 default clocking dclk @ (posedge clk);
 63 
 64 endclocking
 65 //=================================================
 66 // Test Vector generation
 67 //=================================================
 68 initial begin
 69   miff.tb.cb.reset <= 1;
 70   miff.tb.cb.ce <= 1'b0;
 71   miff.tb.cb.we <= 1'b0;
 72   miff.tb.cb.addr <= 0;
 73   miff.tb.cb.datai <= 0;
 74    ##1  miff.tb.cb.reset <= 0;
 75   for (int i = 0; i < 3; i ++ ) begin
 76      ##1  miff.tb.cb.ce <= 1'b1;
 77     miff.tb.cb.we <= 1'b1;
 78     miff.tb.cb.addr <= i;
 79     miff.tb.cb.datai <= $random;
 80      ##3  miff.tb.cb.ce <= 1'b0;
 81     $display ("@%0dns Write access address %x, data %x",
 82       $time,miff.addr,miff.datai);
 83   end
 84   for (int i = 0; i < 3; i ++ ) begin
 85      ##1  miff.tb.cb.ce <= 1'b1;
 86     miff.tb.cb.we <= 1'b0;
 87     miff.tb.cb.addr <= i;
 88      ##3  miff.tb.cb.ce <= 1'b0;
 89     $display ("@%0dns Read access address %x, data %x",
 90       $time,miff.addr,miff.datao);
 91   end
 92    #10  $finish;
 93 end
 94 
 95 endmodule

A interface file can consit of ports, modports, clocking blocks and internal signals as shown in example.

 @90ns Write access address 00, data 24
 @170ns Write access address 01, data 81
 @250ns Write access address 02, data 09
 @330ns Read access address 00, data 24
 @410ns Read access address 01, data 81
 @490ns Read access address 02, data 09

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Deepak Kumar Tala - All rights reserved

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