When RTL is already written and it becomes responsibilty of a verification engineer to add assertion. And RTL designer does not want verification engineer to modify his RTL for the sake of adding assertion then, bind feature of SystemVerilog comes for rescue.

One can write all the assertion he or she wants to write in a seprate file and using bind, he or she can bind the ports of his assertion file with the port/signals of the RTL in his testbench code. What a cool feature.

A Bind feature can be used in following places.

• module
• interface
• compilation unit scope

There are two forms of binding

• Multi Instance : In this form, binding is done to multiple instance of a module.
• Single Instance : In this form, binding is done to single instance of a module.

Below example shows the usage of bind feature of SystemVerilog.

DUT File

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 //   DUT With assertions
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module bind_assertion(
  5   input wire clk,req,reset, 
  6   output reg gnt);
  7 //=================================================
  8 // Actual DUT RTL
  9 //=================================================
 10 always @ (posedge clk)
 11   gnt <= req;
 12 
 13 endmodule

Assertion File

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 //   Assertion Verification IP
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module assertion_ip(input wire clk_ip, req_ip,reset_ip,gnt_ip);
  5 //=================================================
  6 // Sequence Layer
  7 //=================================================
  8 sequence req_gnt_seq;
  9   (~req_ip & gnt_ip)  ##1  (~req_ip & ~gnt_ip);
 10 endsequence
 11 //=================================================
 12 // Property Specification Layer
 13 //=================================================
 14 property req_gnt_prop;
 15   @ (posedge clk_ip) 
 16     disable iff (reset_ip)
 17       req_ip |=> req_gnt_seq;
 18 endproperty
 19 //=================================================
 20 // Assertion Directive Layer
 21 //=================================================
 22 req_gnt_assert : assert property (req_gnt_prop)
 23                  else
 24                  $display("@%0dns Assertion Failed", $time);
 25 
 26 endmodule

Binding File

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 //  Binding File 
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module binding_module();
  5 //=================================================
  6 // Bind by Module name : This will bind all instance
  7 // of DUT
  8 //=================================================
  9 // Here RTL : stands for design under test
 10 //      VIP : Assertion file
 11 //   RTL Module Name  VIP module Name   Instance Name
 12 bind bind_assertion   assertion_ip      U_assert_ip (
 13 // .vip port (RTL port)
 14  .clk_ip   (clk),
 15  .req_ip   (req),
 16  .reset_ip (reset),
 17  .gnt_ip   (gnt)
 18 );
 19 //=================================================
 20 // Bind by instance name : This will bind only instance
 21 //  names in list
 22 //=================================================
 23 // Here RTL : stands for design under test
 24 //      VIP : Assertion file
 25 //     RTL Module Name Instance Path               VIP module Name Instance Name
 26 //bind bind_assertion :$root.bind_assertion_tb.dut assertion_ip    U_assert_ip (
 27 // .vip port (RTL port)
 28 // .clk_ip   (clk),
 29 // .req_ip   (req),
 30 // .reset_ip (reset),
 31 // .gnt_ip   (gnt)
 32 //);
 33 //=================================================
 34 
 35 endmodule

Testbench File

  1 //+++++++++++++++++++++++++++++++++++++++++++++++
  2 //   Testbench Code
  3 //+++++++++++++++++++++++++++++++++++++++++++++++
  4 `include "assertion_ip.sv"
  5 `include "bind_assertion.sv"
  6 `include "binding_module.sv"
  7 
  8 module bind_assertion_tb();
  9 
 10 reg clk = 0;
 11 reg reset, req = 0;
 12 wire gnt;
 13 
 14 always  #3  clk ++;
 15 
 16 initial begin
 17   reset <= 1;
 18    #20  reset <= 0;
 19   // Make the assertion pass
 20    #100  @ (posedge clk) req  <= 1;
 21   @ (posedge clk) req <= 0;
 22   // Make the assertion fail
 23    #100  @ (posedge clk) req  <= 1;
 24   repeat (5) @ (posedge clk);
 25   req <= 0;
 26    #10  $finish;
 27 end
 28 
 29 bind_assertion dut (clk,req,reset,gnt);
 30 
 31 endmodule

 "assertion_ip.sv", 22: bind_assertion_tb.dut.U_assert_ip.req_gnt_assert:
  started at 237s failed at 243s
         Offending '((~req_ip) & gnt_ip)'
 @243ns Assertion Failed
 "assertion_ip.sv", 22: bind_assertion_tb.dut.U_assert_ip.req_gnt_assert: 
  started at 243s failed at 249s
         Offending '((~req_ip) & gnt_ip)'
 @249ns Assertion Failed
 "assertion_ip.sv", 22: bind_assertion_tb.dut.U_assert_ip.req_gnt_assert: 
  started at 249s failed at 255s
         Offending '((~req_ip) & gnt_ip)'
 @255ns Assertion Failed
 "assertion_ip.sv", 22: bind_assertion_tb.dut.U_assert_ip.req_gnt_assert: 
  started at 255s failed at 261s
         Offending '((~req_ip) & gnt_ip)'
 @261ns Assertion Failed
 $finish called from file "bind_assertion_tb.sv", line 26.

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Deepak Kumar Tala - All rights reserved

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