There are times when we want to check signals or variables from two or more clock domains. As such SystemVerilog provides multi clock support in both sequence and property declaration.

Multiclocked sequences are built by concatenating singly clocked subsequences using the single-delay concatenation operator ##1. This operator is nonoverlapping and synchronizes between the clocks of the two sequences. The single delay indicated by ##1 is understood to be from the end point of the first sequence, which occurs at a tick of the first clock, to the nearest strictly subsequent tick of the second clock, where the second sequence begins.

Below examples shows this is done.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 //   DUT With assertions
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module multi_clock_seq_assertion();
  5 logic clk1 = 0;
  6 logic clk2 = 0;
  7 logic req;
  8 logic gnt;
  9 //=================================================
 10 // Sequence Specification Layer
 11 //=================================================
 12 sequence multi_clock_seq;
 13    @(posedge clk1) req  ##1  @(posedge clk2) gnt;
 14 endsequence
 15 //=================================================
 16 // Property Specification Layer
 17 //=================================================
 18 property multi_clock_prop;
 19   @ (posedge clk1)
 20       req |-> multi_clock_seq;
 21 endproperty
 22 //=================================================
 23 // Assertion Directive Layer
 24 //=================================================
 25 multi_clock_assert : assert property (multi_clock_prop);
 26 //=================================================
 27 // Here gnt is driven with respect to CLK2
 28 //=================================================
 29 initial begin
 30    #20  gnt <= 1;
 31    #120  gnt <= 0;
 32 end
 33 //+++++++++++++++++++++++++++++++++++++++++++++++++
 34 //  Assertion testing code
 35 //+++++++++++++++++++++++++++++++++++++++++++++++++
 36 initial begin
 37   // Make the assertion pass
 38   req  <= 0; gnt <= 0;
 39    #100  @ (posedge clk1) req  <= 1;
 40   repeat (20) @ (posedge clk1);
 41   req <= 0;
 42    #10  $finish;
 43 end
 44 
 45 always  #1    clk1 ++;
 46 always #6.1 clk2 ++;
 47 
 48 endmodule

 "multi_clock_seq_assertion.sv", 25: 
 multi_clock_seq_assertion.multi_clock_assert: started at 139s failed at 150s
         Offending 'gnt'
 "multi_clock_seq_assertion.sv", 25: 
 multi_clock_seq_assertion.multi_clock_assert: started at 141s failed at 150s
         Offending 'gnt'
 $finish called from file "multi_clock_seq_assertion.sv", line 42.

A multi clock sequence in itself is a kind of multi clock property. Below example is slit variation of multi clock sequence example seen earlier.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 //   DUT With assertions
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module multi_clock_prop_assertion();
  5 logic clk1 = 0;
  6 logic clk2 = 0;
  7 logic req;
  8 logic gnt;
  9 //=================================================
 10 // Property Specification Layer
 11 //=================================================
 12 property multi_clock_prop;
 13   @(posedge clk1) req |->  ##1  @(posedge clk2) gnt;
 14 endproperty
 15 //=================================================
 16 // Assertion Directive Layer
 17 //=================================================
 18 multi_clock_assert : assert property (multi_clock_prop);
 19 //=================================================
 20 // Here gnt is driven with respect to CLK2
 21 //=================================================
 22 initial begin
 23    #20  gnt <= 1;
 24    #120  gnt <= 0;
 25 end
 26 //+++++++++++++++++++++++++++++++++++++++++++++++++
 27 //  Assertion testing code
 28 //+++++++++++++++++++++++++++++++++++++++++++++++++
 29 initial begin
 30   // Make the assertion pass
 31   req  <= 0; gnt <= 0;
 32    #100  @ (posedge clk1) req  <= 1;
 33   repeat (20) @ (posedge clk1);
 34   req <= 0;
 35    #10  $finish;
 36 end
 37 
 38 always  #1    clk1 ++;
 39 always #6.1 clk2 ++;
 40 
 41 endmodule

 "multi_clock_prop_assertion.sv", 18: 
 multi_clock_prop_assertion.multi_clock_assert: started at 139s failed at 150s
         Offending 'gnt'
 "multi_clock_prop_assertion.sv", 18: 
 multi_clock_prop_assertion.multi_clock_assert: started at 141s failed at 150s
         Offending 'gnt'
 $finish called from file "multi_clock_prop_assertion.sv", line 35.

Copyright © 1998-2025

Deepak Kumar Tala - All rights reserved

Do you have any Comment? mail me at:deepak@asic-world.com