|
|
|
|
|
|
|
|
|
|
|
|
if..else
|
|
|
A property is an if...else kind if it has either the form |
|
|
|
|
|
if (expression_or_dist) property_expr1
|
|
|
|
|
|
or of the form |
|
|
|
|
|
if (expression_or_dist) property_expr1
else property_expr2
|
|
|
|
|
|
A property of the first form evaluates to true if, and only if, either expression_or_dist evaluates to false or property_expr1 evaluates to true. A property of the second form evaluates to true if, and only if, either expression_or_dist evaluates to true and property_expr1 evaluates to true or expression_or_dist evaluates to false and property_expr2 evaluates to true. Below example shows the usage of the same. |
|
|
|
|
|
Real usage example would be, check if command is read, if yes then check property read_property else check property write_property. |
|
|
|
|
|
|
|
|
|
|
|
Example : if..else
|
|
|
|
|
|
1 //+++++++++++++++++++++++++++++++++++++++++++++++++
2 // DUT With assertions
3 //+++++++++++++++++++++++++++++++++++++++++++++++++
4 module ifelse_assertion();
5
6 logic req,gnt,clk,check;
7 //=================================================
8 // Clock generator
9 //=================================================
10 initial begin
11 clk = 0;
12 forever #1 clk ++;
13 end
14 //=================================================
15 // Simple DUT behaviour
16 //=================================================
17 logic gnt2;
18 initial begin
19 gnt2 <= 0; gnt <= 0;
20 end
21 always @ (posedge clk)
22 begin
23 gnt2 <= req;
24 gnt <= gnt2;
25 end
26 //=================================================
27 // Test Vector generation
28 //=================================================
29 initial begin
30 req <= 0;check <= 0;
31 #3 req <= 1;
32 #10 req <= 0;check <= 1;
33 #3 req <= 1;
34 #5 req <= 0;
35 #1 $finish;
36 end
37 //=================================================
38 // A ifelse property
39 //=================================================
40 property delay1;
41 req ##1 gnt;
42 endproperty
43 property delay2;
44 req ##2 gnt;
45 endproperty
46 // See the OR operator
47 property ifelse_prop;
48 @ (posedge clk)
49 if (check)
50 delay1
51 else
52 delay2;
53 endproperty
54 //=================================================
55 // Assertion Directive Layer
56 //=================================================
57 ifelse_assert : assert property (ifelse_prop);
58
59 endmodule
You could download file ifelse_assertion.sv here
|
|
|
|
|
|
Simulation : if..else
|
|
|
|
|
|
"ifelse_assertion.sv", 57: ifelse_assertion.ifelse_assert:
started at 1s failed at 1s
Offending 'req'
"ifelse_assertion.sv", 57: ifelse_assertion.ifelse_assert:
started at 3s failed at 3s
Offending 'req'
"ifelse_assertion.sv", 57: ifelse_assertion.ifelse_assert:
started at 15s failed at 15s
Offending 'req'
"ifelse_assertion.sv", 57: ifelse_assertion.ifelse_assert:
started at 17s failed at 19s
Offending 'gnt'
$finish called from file "ifelse_assertion.sv", line 35.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Copyright © 1998-2014 |
Deepak Kumar Tala - All rights reserved |
Do you have any Comment? mail me at:deepak@asic-world.com
|
|