One can have local variables inside a sequence or a property. This local variables can be assigned values and can be sampled later. Example below shows how this is done.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 //   DUT With assertions
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module localvar_assertion();
  5 
  6 logic clk = 0;
  7 always  #1  clk ++;
  8 
  9 logic [7:0] portin, portout;
 10 logic       in_en, out_en;
 11 //=================================================
 12 // Sequence Layer
 13 //=================================================
 14 sequence local_var_seq;
 15    logic [7:0] lport;
 16    (in_en, lport = portin) ##[1:5] 
 17       (out_en and lport == portout);
 18 endsequence
 19 //=================================================
 20 // Property Specification Layer
 21 //=================================================
 22 property local_var_prop;
 23   @ (posedge clk) 
 24       in_en |-> local_var_seq;
 25 endproperty
 26 //=================================================
 27 // Assertion Directive Layer
 28 //=================================================
 29 local_var_assert : assert property (local_var_prop);
 30 //=================================================
 31 // Simple DUT logic 
 32 //=================================================
 33 always @ (posedge clk)
 34 begin
 35   portout <= (portin < 4) ? portin : portin + 1;
 36   out_en  <= in_en;
 37 end
 38 //=================================================
 39 // Generate input vectors
 40 //=================================================
 41 initial begin
 42   in_en <= 0; out_en <= 0;
 43   portin <= 0; portout <= 0;
 44   repeat (20) @ (posedge clk);
 45   for (int i =0 ; i < 8; i ++) begin
 46     @ (posedge clk);
 47     in_en <= 1;
 48     portin <= i;
 49     @ (posedge clk);
 50     in_en <= 0;
 51     portin <= 0;
 52   end
 53    #30  $finish;
 54 end
 55 
 56 endmodule

 Assertion error.
 Time: 69 ns Started: 59 ns  
 localvar_assertion.local_var_assert Line: 26
 Assertion error.
 Time: 73 ns Started: 63 ns  
 localvar_assertion.local_var_assert Line: 26
 Assertion error.
 Time: 77 ns Started: 67 ns  
 localvar_assertion.local_var_assert Line: 26
 Assertion error.
 Time: 81 ns Started: 71 ns  
 localvar_assertion.local_var_assert Line: 26

Tasks, task methods, void functions, void function methods, and system tasks can be called at the end of a successful match of a sequence. The subroutine calls, like local variable assignments, appear in the commaseparated list that follows the sequence. The subroutine calls are said to be attached to the sequence. The sequence and the list that follows are enclosed in parentheses.

All subroutine calls attached to a sequence are executed at every successful match of the sequence.

  1 //+++++++++++++++++++++++++++++++++++++++++++++++++
  2 //   DUT With assertions
  3 //+++++++++++++++++++++++++++++++++++++++++++++++++
  4 module subroutine_assertion();
  5 
  6 logic clk = 0;
  7 always  #1  clk ++;
  8 
  9 logic [7:0] portin, portout;
 10 logic       in_en, out_en;
 11 //=================================================
 12 // Sequence Layer
 13 //=================================================
 14 sequence local_var_seq;
 15    logic [7:0] lport;
 16    (in_en, lport = portin) ##[1:5] 
 17       (out_en and lport == portout, 
 18         $display ("@%0dns Input port %0d and Output port %0d match", 
 19          $time, lport,portout));
 20 endsequence
 21 //=================================================
 22 // Property Specification Layer
 23 //=================================================
 24 property local_var_prop;
 25   @ (posedge clk) 
 26       in_en |-> local_var_seq;
 27 endproperty
 28 //=================================================
 29 // Assertion Directive Layer
 30 //=================================================
 31 local_var_assert : assert property (local_var_prop);
 32 //=================================================
 33 // Simple DUT logic 
 34 //=================================================
 35 always @ (posedge clk)
 36 begin
 37   portout <= (portin < 4) ? portin : portin + 1;
 38   out_en  <= in_en;
 39 end
 40 //=================================================
 41 // Generate input vectors
 42 //=================================================
 43 initial begin
 44   in_en <= 0; out_en <= 0;
 45   portin <= 0; portout <= 0;
 46   repeat (20) @ (posedge clk);
 47   for (int i =0 ; i < 8; i ++) begin
 48     @ (posedge clk);
 49     in_en <= 1;
 50     portin <= i;
 51     @ (posedge clk);
 52     in_en <= 0;
 53     portin <= 0;
 54   end
 55    #30  $finish;
 56 end
 57 
 58 endmodule

 @45ns Input port 0 and Output port 0 match
 @49ns Input port 1 and Output port 1 match
 @53ns Input port 2 and Output port 2 match
 @57ns Input port 3 and Output port 3 match
 Assertion error.
 Time: 69 ns Started: 59 ns  localvar_assertion.local_var_assert Line: 28
 Assertion error.
 Time: 73 ns Started: 63 ns  localvar_assertion.local_var_assert Line: 28
 Assertion error.
 Time: 77 ns Started: 67 ns  localvar_assertion.local_var_assert Line: 28
 Assertion error.
 Time: 81 ns Started: 71 ns  localvar_assertion.local_var_assert Line: 28

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