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Sequential Logic Using UDP
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D Latch
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1 primitive latch_udp(q, clock, data) ;
2 output q; reg q ;
3 input clock, data;
4 table
5 // clock data q q+
6 0 1 : ? : 1 ;
7 0 0 : ? : 0 ;
8 1 ? : ? : - ; // - = no change
9 endtable
10 endprimitive
You could download file latch_udp.v here
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D Flip Flop
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1 //-----------------------------------------------------
2 // Design Name : dff_udp
3 // File Name : dff_udp.v
4 // Function : D Flip Flop
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 primitive dff_udp (q,clk,d);
8 input clk,d;
9 output q;
10 reg q;
11 table
12 // clk d : q : q+
13 r 0 : ? : 0 ;
14 r 1 : ? : 1 ;
15 f ? : ? : - ;
16 ? * : ? : - ;
17 endtable
18 endprimitive
You could download file dff_udp.v here
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SR Flip Flop
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1 primitive srff_udp (q,s,r);
2 output q;
3 input s,r;
4
5 reg q;
6
7 initial q = 1'b1;
8
9 table
10 // s r q q+
11 1 0 : ? : 1 ;
12 f 0 : 1 : - ;
13 0 r : ? : 0 ;
14 0 f : 0 : - ;
15 1 1 : ? : 0 ;
16 endtable
17
18 endprimitive
You could download file srff_udp.v here
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JK Flip Flop
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1 //-----------------------------------------------------
2 // Design Name : jkff_udp
3 // File Name : jkff_udp.v
4 // Function : JK Flip Flop Using UDP
5 // Coder : Deepak Kumar Tala
6 //-----------------------------------------------------
7 primitive jkff_udp (q,clk,j,k);
8 input clk,j,k;
9 output q;
10 reg q;
11 table
12 // clk j k : q : q+
13 r 0 0 : ? : - ;
14 r 0 1 : ? : 0 ;
15 r 1 0 : ? : 1 ;
16 r 1 1 : 0 : 1 ;
17 r 1 1 : 1 : 0 ;
18 f ? ? : ? : - ;
19 ? * ? : ? : - ;
20 ? ? * : ? : - ;
21 endtable
22 endprimitive
You could download file jkff_udp.v here
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Copyright © 1998-2025 |
Deepak Kumar Tala - All rights reserved |
Do you have any Comment? mail me at:deepak@asic-world.com
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