1 //-----------------------------------------------------
  2 // Design Name : ram_dp_ar_aw
  3 // File Name   : ram_dp_ar_aw.v
  4 // Function    : Asynchronous read write RAM
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module ram_dp_ar_aw (
  8 address_0 , // address_0 Input
  9 data_0    , // data_0 bi-directional
 10 cs_0      , // Chip Select
 11 we_0      , // Write Enable/Read Enable
 12 oe_0      , // Output Enable
 13 address_1 , // address_1 Input
 14 data_1    , // data_1 bi-directional
 15 cs_1      , // Chip Select
 16 we_1      , // Write Enable/Read Enable
 17 oe_1        // Output Enable
 18 ); 
 19 
 20 parameter DATA_WIDTH = 8 ;
 21 parameter ADDR_WIDTH = 8 ;
 22 parameter RAM_DEPTH = 1 << ADDR_WIDTH;
 23 
 24 //--------------Input Ports----------------------- 
 25 input [ADDR_WIDTH-1:0] address_0 ;
 26 input cs_0 ;
 27 input we_0 ;
 28 input oe_0 ; 
 29 input [ADDR_WIDTH-1:0] address_1 ;
 30 input cs_1 ;
 31 input we_1 ;
 32 input oe_1 ; 
 33 
 34 //--------------Inout Ports----------------------- 
 35 inout [DATA_WIDTH-1:0] data_0 ; 
 36 inout [DATA_WIDTH-1:0] data_1 ;
 37 
 38 //--------------Internal variables---------------- 
 39 reg [DATA_WIDTH-1:0] data_0_out ; 
 40 reg [DATA_WIDTH-1:0] data_1_out ;
 41 reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
 42 
 43 //--------------Code Starts Here------------------ 
 44 // Memory Write Block 
 45 // Write Operation : When we_0 = 1, cs_0 = 1
 46 always @ (address_0 or cs_0 or we_0 or data_0
 47 or address_1 or cs_1 or we_1 or data_1)
 48 begin : MEM_WRITE
 49   if ( cs_0 && we_0 ) begin
 50      mem[address_0] <= data_0;
 51   end else if  (cs_1 && we_1) begin
 52      mem[address_1] <= data_1;
 53   end
 54 end
 55 
 56 // Tri-State Buffer control 
 57 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
 58 assign data_0 = (cs_0 && oe_0 &&  ! we_0) ? data_0_out : 8'bz; 
 59 
 60 // Memory Read Block 
 61 // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
 62 always @ (address_0 or cs_0 or we_1 or oe_0)
 63 begin : MEM_READ_0
 64   if (cs_0 &&  ! we_0 && oe_0) begin
 65     data_0_out <= mem[address_0]; 
 66   end else begin
 67     data_0_out <= 0; 
 68   end
 69 end 
 70 
 71 //Second Port of RAM
 72 // Tri-State Buffer control 
 73 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
 74 assign data_1 = (cs_1 && oe_1 &&  ! we_1) ? data_1_out : 8'bz; 
 75 // Memory Read Block 1 
 76 // Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1
 77 always @ (address_1 or cs_1 or we_1 or oe_1)
 78 begin : MEM_READ_1
 79   if (cs_1 &&  ! we_1 && oe_1) begin
 80     data_1_out <= mem[address_1]; 
 81   end else begin
 82     data_1_out <= 0; 
 83   end
 84 end
 85 
 86 endmodule // End of Module ram_dp_ar_aw

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Deepak Kumar Tala - All rights reserved

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