Below code is 16-bit CRC-CCITT implementation, with following features

• Width = 16 bits
• Truncated polynomial = 0x1021
• Initial value = 0xFFFF
• Input data is NOT reflected
• Output CRC is NOT reflected
• No XOR is performed on the output CRC

  1 //-----------------------------------------------------
  2 // Design Name : parallel_crc_ccitt
  3 // File Name   : parallel_crc.v
  4 // Function    : CCITT Parallel CRC
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module parallel_crc_ccitt (
  8 clk     ,
  9 reset   ,
 10 enable  ,
 11 init    , 
 12 data_in , 
 13 crc_out
 14 );
 15 //-----------Input Ports---------------
 16 input clk     ;
 17 input reset   ;
 18 input enable  ;
 19 input init    ;
 20 input [7:0] data_in ;
 21 //-----------Output Ports---------------
 22 output [15:0] crc_out;
 23 //------------Internal Variables--------
 24 reg [15:0]   crc_reg;
 25 wire [15:0]  next_crc;
 26 //-------------Code Start-----------------
 27 assign crc_out = crc_reg;
 28 // CRC Control logic
 29 always @ (posedge clk)
 30 if (reset) begin
 31   crc_reg <= 16'hFFFF;
 32 end else if (enable) begin
 33   if (init) begin
 34      crc_reg <= 16'hFFFF;
 35   end else begin
 36      crc_reg <= next_crc;
 37   end
 38 end
 39 // Parallel CRC calculation
 40 assign next_crc[0] = data_in[7] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[11];
 41 assign next_crc[1] = data_in[1] ^ crc_reg[5];
 42 assign next_crc[2] = data_in[2] ^ crc_reg[6];
 43 assign next_crc[3] = data_in[3] ^ crc_reg[7];
 44 assign next_crc[4] = data_in[4] ^ crc_reg[8];
 45 assign next_crc[5] = data_in[7] ^ data_in[5] ^ data_in[0] ^ crc_reg[4] ^ crc_reg[9] ^ crc_reg[11];
 46 assign next_crc[6] = data_in[6] ^ data_in[1] ^ crc_reg[5] ^ crc_reg[10];
 47 assign next_crc[7] = data_in[7] ^ data_in[2] ^ crc_reg[6] ^ crc_reg[11];
 48 assign next_crc[8] = data_in[3] ^ crc_reg[0] ^ crc_reg[7];
 49 assign next_crc[9] = data_in[4] ^ crc_reg[1] ^ crc_reg[8];
 50 assign next_crc[10] = data_in[5] ^ crc_reg[2] ^ crc_reg[9];
 51 assign next_crc[11] = data_in[6] ^ crc_reg[3] ^ crc_reg[10];
 52 
 53 endmodule

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Deepak Kumar Tala - All rights reserved

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