1 //-----------------------------------------------------
  2 // Design Name : mux_2to1_gates
  3 // File Name   : mux_2to1_gates.v
  4 // Function    : 2:1 Mux using Gate Primitives
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module mux_2to1_gates(a,b,sel,y);
  8 input a,b,sel;
  9 output y;
 10 
 11 wire sel,a_sel,b_sel;
 12 
 13 not U_inv (inv_sel,sel);
 14 and U_anda (asel,a,inv_sel),
 15     U_andb (bsel,b,sel);
 16 or U_or (y,asel,bsel);
 17 
 18 endmodule

  1 //-----------------------------------------------------
  2 // Design Name : mux_4to1_gates
  3 // File Name   : mux_4to1_gates.v
  4 // Function    : 4:1 Mux Using Gates
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module mux_4to1_gates(a,b,c,d,sel,y);
  8 input a,b,c,d;
  9 input [1:0] sel;
 10 output y;
 11 
 12 wire mux_1,mux_2;
 13 
 14 mux_2to1_gates U_mux1 (a,b,sel[0],mux_1),
 15                U_mux2 (c,d,sel[0],mux_2),
 16                U_mux3 (mux_1,mux_2,sel[1],y);
 17 
 18 endmodule

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Deepak Kumar Tala - All rights reserved

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