1 //-----------------------------------------------------
  2 // Design Name : lfsr
  3 // File Name   : lfsr.v
  4 // Function    : Linear feedback shift register
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module lfsr    (
  8 out             ,  // Output of the counter
  9 enable          ,  // Enable  for counter
 10 clk             ,  // clock input
 11 reset              // reset input
 12 );
 13 
 14 //----------Output Ports--------------
 15 output [7:0] out;
 16 //------------Input Ports--------------
 17 input [7:0] data;
 18 input enable, clk, reset;
 19 //------------Internal Variables--------
 20 reg [7:0] out;
 21 wire        linear_feedback;
 22 
 23 //-------------Code Starts Here-------
 24 assign linear_feedback =  ! (out[7] ^ out[3]);
 25 
 26 always @(posedge clk)
 27 if (reset) begin // active high reset
 28   out <= 8'b0 ;
 29 end else if (enable) begin
 30   out <= {out[6],out[5],
 31           out[4],out[3],
 32           out[2],out[1],
 33           out[0], linear_feedback};
 34 end 
 35 
 36 endmodule // End Of Module counter

  1 `define WIDTH 8 
  2 module lfsr_updown (
  3 clk       ,   // Clock input
  4 reset     ,   // Reset input
  5 enable    ,   // Enable input
  6 up_down   ,   // Up Down input
  7 count     ,   // Count output
  8 overflow      // Overflow output
  9 );
 10 
 11  input clk;
 12  input reset;
 13  input enable; 
 14  input up_down;
 15 
 16  output [`WIDTH-1 : 0] count;
 17  output overflow;
 18 
 19  reg [`WIDTH-1 : 0] count;
 20 
 21  assign overflow = (up_down) ? (count == {{`WIDTH-1{1'b0}}, 1'b1}) : 
 22                                (count == {1'b1, {`WIDTH-1{1'b0}}}) ;
 23 
 24  always @(posedge clk)
 25  if (reset) 
 26     count <= {`WIDTH{1'b0}};
 27  else if (enable) begin
 28     if (up_down) begin
 29       count <= {~(^(count & `WIDTH'b01100011)),count[`WIDTH-1:1]};
 30     end else begin
 31       count <= {count[`WIDTH-2:0],~(^(count &  `WIDTH'b10110001))};
 32     end
 33  end
 34 
 35 endmodule

  1 module tb();
  2  reg clk;
  3  reg reset;
  4  reg enable;
  5  reg up_down;
  6 
  7  wire [`WIDTH-1 : 0] count;
  8  wire overflow;
  9 
 10 initial begin
 11   $monitor("rst %b en %b updown %b cnt %b overflow %b",
 12      reset,enable,up_down,count, overflow);
 13   clk = 0;
 14   reset = 1;
 15   enable = 0;
 16   up_down = 0;
 17    #10  reset = 0;
 18    #1  enable = 1;
 19    #20  up_down = 1;
 20    #30  $finish;
 21 end
 22 
 23 always  #1  clk = ~clk;
 24 
 25 lfsr_updown U(
 26 .clk      ( clk      ),
 27 .reset    ( reset    ),
 28 .enable   ( enable   ),
 29 .up_down  ( up_down  ),
 30 .count    ( count    ),
 31 .overflow ( overflow )
 32 );
 33 
 34 endmodule

Copyright © 1998-2014

Deepak Kumar Tala - All rights reserved

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