This module divides the input clock frequency by 3

  1 //-----------------------------------------------------
  2 // Design Name : divide_by_3 
  3 // File Name   : divide_by_3.v
  4 // Function    : Divide By 3
  5 // Coder       : Deepak Kumar Tala
  6 //-----------------------------------------------------
  7 module divide_by_3 (
  8 clk_in       , //Input Clock
  9 reset        , // Reset Input
 10 clk_out        // Output Clock
 11 );
 12 //-----------Input Ports---------------
 13 input clk_in;
 14 input  reset;
 15 //-----------Output Ports---------------
 16 output clk_out;
 17 //------------Internal Variables--------
 18 reg [1:0] pos_cnt;
 19 reg [1:0] neg_cnt;
 20 //-------------Code Start-----------------
 21 // Posedge counter
 22 always @ (posedge clk_in)
 23 if (reset) begin
 24   pos_cnt <= 0;
 25 end else begin
 26   pos_cnt <= (pos_cnt == 2) ? 0 : pos_cnt + 1;
 27 end
 28 // Neg edge counter
 29 always @ (negedge clk_in)
 30 if (reset) begin
 31   neg_cnt <= 0;
 32 end else begin
 33   neg_cnt <= (neg_cnt == 2) ? 0 : neg_cnt + 1;
 34 end
 35 
 36 assign clk_out = ((pos_cnt  ! = 2) && (neg_cnt  ! = 2));
 37 
 38 endmodule
 39 
 40 // Testbench to check the divide_by_3 logic
 41 module test();
 42 reg reset, clk_in;
 43 wire clk_out;
 44 divide_by_3 U (
 45   .clk_in (clk_in),
 46   .reset  (reset),
 47   .clk_out (clk_out)
 48 );
 49 
 50 initial begin
 51    clk_in = 0;
 52    reset = 0;
 53     #2  reset = 1;
 54     #2  reset = 0;
 55     #100  $finish;
 56 end
 57 
 58 always  #1  clk_in = ~clk_in;
 59 
 60 endmodule

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