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1 //=============================================
2 // Function : Synchronous (single clock) FIFO
3 // Coder : Deepak Kumar Tala
4 // Date : 31-October-2005
5 //=============================================
6 module syn_fifo #(parameter DATA_WIDTH = 8,
7 parameter ADDR_WIDTH = 8,
8 parameter RAM_DEPTH = (1 << ADDR_WIDTH))(
9 input wire clk , // Clock input
10 input wire rst , // Active high reset
11 input wire wr_cs , // Write chip select
12 input wire rd_cs , // Read chipe select
13 input wire [DATA_WIDTH-1:0] data_in , // Data input
14 input wire rd_en , // Read enable
15 input wire wr_en , // Write Enable
16 output reg [DATA_WIDTH-1:0] data_out , // Data Output
17 output wire empty , // FIFO empty
18 output wire full // FIFO full
19 );
20 //-----------Internal variables-------------------
21 reg [ADDR_WIDTH-1:0] wr_pointer;
22 reg [ADDR_WIDTH-1:0] rd_pointer;
23 reg [ADDR_WIDTH :0] status_cnt;
24 wire [DATA_WIDTH-1:0] data_ram ;
25 //-----------Variable assignments---------------
26 assign full = (status_cnt == (RAM_DEPTH-1));
27 assign empty = (status_cnt == 0);
28 //-----------Code Start---------------------------
29 always_ff @ (posedge clk iff rst == 0 , posedge rst)
30 begin : WRITE_POINTER
31 if (rst) begin
32 wr_pointer <= 0;
33 end else if (wr_cs && wr_en ) begin
34 wr_pointer <= wr_pointer + 1;
35 end
36 end
37
38 always_ff @ (posedge clk iff rst == 0 , posedge rst)
39 begin : READ_POINTER
40 if (rst) begin
41 rd_pointer <= 0;
42 end else if (rd_cs && rd_en ) begin
43 rd_pointer <= rd_pointer + 1;
44 end
45 end
46
47 always_ff @ (posedge clk iff rst == 0 , posedge rst)
48 begin : READ_DATA
49 if (rst) begin
50 data_out <= 0;
51 end else if (rd_cs && rd_en ) begin
52 data_out <= data_ram;
53 end
54 end
55
56 always_ff @ (posedge clk iff rst == 0 , posedge rst)
57 begin : STATUS_COUNTER
58 if (rst) begin
59 status_cnt <= 0;
60 // Read but no write.
61 end else if ((rd_cs && rd_en) && ! (wr_cs && wr_en)
62 && (status_cnt ! = 0)) begin
63 status_cnt <= status_cnt - 1;
64 // Write but no read.
65 end else if ((wr_cs && wr_en) && ! (rd_cs && rd_en)
66 && (status_cnt ! = RAM_DEPTH)) begin
67 status_cnt <= status_cnt + 1;
68 end
69 end
70
71 ram_dp_ar_aw #(DATA_WIDTH,ADDR_WIDTH)DP_RAM (
72 .address_0 (wr_pointer) , // address_0 input
73 .data_0 (data_in) , // data_0 bi-directional
74 .cs_0 (wr_cs) , // chip select
75 .we_0 (wr_en) , // write enable
76 .oe_0 (1'b0) , // output enable
77 .address_1 (rd_pointer) , // address_q input
78 .data_1 (data_ram) , // data_1 bi-directional
79 .cs_1 (rd_cs) , // chip select
80 .we_1 (1'b0) , // Read enable
81 .oe_1 (rd_en) // output enable
82 );
83
84 endmodule
You could download file sv_examples here
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