1 //===========================================
  2 // Function : Synchronous read write RAM
  3 // Coder    : Deepak Kumar Tala
  4 // Date     : 1-Nov-2005
  5 //===========================================
  6 module ram_dp_sr_sw #(parameter DATA_WIDTH = 8,
  7                   parameter ADDR_WIDTH = 8,
  8                   parameter RAM_DEPTH = (1 << ADDR_WIDTH))(
  9 input  wire                  clk       , // Clock Input
 10 input  wire [ADDR_WIDTH-1:0] address_0 , // address_0 Input
 11 inout  wire [DATA_WIDTH-1:0] data_0    , // data_0 bi-directional
 12 input  wire                  cs_0      , // Chip Select
 13 input  wire                  we_0      , // Write Enable/Read Enable
 14 input  wire                  oe_0      , // Output Enable
 15 input  wire [ADDR_WIDTH-1:0] address_1 , // address_1 Input
 16 inout  wire [DATA_WIDTH-1:0] data_1    , // data_1 bi-directional
 17 input  wire                  cs_1      , // Chip Select
 18 input  wire                  we_1      , // Write Enable/Read Enable
 19 input  wire                  oe_1        // Output Enable
 20 ); 
 21 //--------------Internal variables---------------- 
 22 reg [DATA_WIDTH-1:0] data_0_out ; 
 23 reg [DATA_WIDTH-1:0] data_1_out ;
 24 // Use Associative array to save memory footprint
 25 typedef reg [ADDR_WIDTH-1:0] mem_addr;
 26 reg [DATA_WIDTH-1:0] mem [mem_addr];
 27 
 28 //--------------Code Starts Here------------------ 
 29 // Memory Write Block 
 30 // Write Operation : When we_0 = 1, cs_0 = 1
 31 always @ (posedge clk)
 32 begin : MEM_WRITE
 33   if ( cs_0 && we_0 ) begin
 34      mem[address_0] = data_0;
 35   end else if (cs_1 && we_1) begin 
 36      mem[address_1] = data_1;
 37   end
 38 end
 39 
 40 // Tri-State Buffer control 
 41 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
 42 assign data_0 = (cs_0 && oe_0 &&  ! we_0) ? data_0_out : 8'bz; 
 43 
 44 // Memory Read Block 
 45 // Read Operation : When we_0 = 0, oe_0 = 1, cs_0 = 1
 46 always @ (posedge clk)
 47 begin : MEM_READ_0
 48   if (cs_0 &&  ! we_0 && oe_0) begin
 49     data_0_out = mem[address_0]; 
 50   end else begin
 51     data_0_out = 0; 
 52   end  
 53 end 
 54 
 55 //Second Port of RAM
 56 // Tri-State Buffer control 
 57 // output : When we_0 = 0, oe_0 = 1, cs_0 = 1
 58 assign data_1 = (cs_1 && oe_1 &&  ! we_1) ? data_1_out : 8'bz; 
 59 // Memory Read Block 1 
 60 // Read Operation : When we_1 = 0, oe_1 = 1, cs_1 = 1
 61 always @ (posedge clk)
 62 begin : MEM_READ_1
 63   if (cs_1 &&  ! we_1 && oe_1) begin
 64     data_1_out = mem[address_1]; 
 65   end else begin
 66     data_1_out = 0;
 67   end
 68 end
 69 
 70 endmodule // End of Module ram_dp_sr_sw

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