Verification Of FIFO Part




		Verification Of FIFO
		In this example, we verify a simple synchronous FIFO. Of course in real life we really don't get to verify a FIFO model, as in companies this are generated using script.

		This testbench will slightly different from what we have seen till now.



		So the verification components are split into following blocks

		Push Generator Pop Generator Push Monitor Pop Monitor Scoreboard SystemVerilog testbench top SystemVerilog Interface file HDL Testbench top

		We are going to have some more components that like reset. Push/Pop Driver, Push/Pop Monitor are going to be part of fifo_driver.sv

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