1 -------------------------------------------------------
  2 -- Design Name : up_counter_load
  3 -- File Name   : up_counter_load.vhd
  4 -- Function    : Up counter with load
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11 
 12 entity up_counter_load is
 13   port (
 14     cout   :out std_logic_vector (7 downto 0); -- Output of the counter
 15     data   :in  std_logic_vector (7 downto 0); -- Parallel load for the counter
 16     load   :in  std_logic;                     -- Parallel load enable
 17     enable :in  std_logic;                     -- Enable counting
 18     clk    :in  std_logic;                     -- Input clock
 19     reset  :in  std_logic                      -- Input reset
 20   );
 21 end entity;
 22 
 23 architecture rtl of up_counter_load is
 24     signal count :std_logic_vector (7 downto 0);
 25 begin
 26     process (clk, reset) begin
 27         if (reset = '1') then
 28             count <= (others=>'0');
 29         elsif (rising_edge(clk)) then
 30             if (load = '1') then
 31                 count <= data;
 32             elsif (enable = '1') then
 33                 count <= count + 1;
 34             end if;
 35         end if;
 36     end process;
 37     cout <= count;
 38 end architecture;

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