1 -------------------------------------------------------
  2 -- Design Name : up_counter
  3 -- File Name   : up_counter.vhd
  4 -- Function    : Up counter
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11 
 12 entity up_counter is
 13     port (
 14         cout   :out std_logic_vector (7 downto 0); -- Output of the counter
 15         enable :in  std_logic;                     -- Enable counting
 16         clk    :in  std_logic;                     -- Input clock
 17         reset  :in  std_logic                      -- Input reset
 18     );
 19 end entity;
 20 
 21 architecture rtl of up_counter is
 22     signal count :std_logic_vector (7 downto 0);
 23 begin
 24     process (clk, reset) begin
 25         if (reset = '1') then
 26             count <= (others=>'0');
 27         elsif (rising_edge(clk)) then
 28             if (enable = '1') then
 29                 count <= count + 1;
 30             end if;
 31         end if;
 32     end process;
 33     cout <= count;
 34 end architecture;

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