Below code is 16-bit CRC-CCITT implementation, with following features

• Width = 16 bits
• Truncated polynomial = 0x1021
• Initial value = 0xFFFF
• Input data is NOT reflected
• Output CRC is NOT reflected
• No XOR is performed on the output CRC

  1 -------------------------------------------------------
  2 -- Design Name : serial_crc_ccitt
  3 -- File Name   : serial_crc.vhd
  4 -- Function    : CCITT Serial CRC
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity serial_crc_ccitt is
 12     port (
 13         clk     :in  std_logic;
 14         reset   :in  std_logic;
 15         enable  :in  std_logic;
 16         init    :in  std_logic;
 17         data_in :in  std_logic;
 18         crc_out :out std_logic_vector (15 downto 0)
 19     );
 20 end entity;
 21 
 22 architecture rtl of serial_crc_ccitt is
 23     signal lfsr  :std_logic_vector (15 downto 0);
 24 begin
 25 
 26    -- Logic to CRC Calculation
 27     process (clk) begin
 28         if (rising_edge(clk)) then
 29             if (reset = '1') then
 30                 lfsr <= (others=>'1');
 31             elsif (enable = '1') then
 32                 if (init = '1') then
 33                     lfsr <=  (others=>'1');
 34                 else
 35                     lfsr(0)  <= data_in xor lfsr(15);
 36                     lfsr(1)  <= lfsr(0);
 37                     lfsr(2)  <= lfsr(1);
 38                     lfsr(3)  <= lfsr(2);
 39                     lfsr(4)  <= lfsr(3);
 40                     lfsr(5)  <= lfsr(4) xor data_in xor lfsr(15);
 41                     lfsr(6)  <= lfsr(5);
 42                     lfsr(7)  <= lfsr(6);
 43                     lfsr(8)  <= lfsr(7);
 44                     lfsr(9)  <= lfsr(8);
 45                     lfsr(10) <= lfsr(9);
 46                     lfsr(11) <= lfsr(10);
 47                     lfsr(12) <= lfsr(11) xor data_in xor lfsr(15);
 48                     lfsr(13) <= lfsr(12);
 49                     lfsr(14) <= lfsr(13);
 50                 end if;
 51             end if;
 52         end if;
 53     end process;
 54 
 55     crc_out <= lfsr;
 56 end architecture;

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Deepak Kumar Tala - All rights reserved

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