1 -------------------------------------------------------
  2 -- Design Name : parity_using_assign
  3 -- File Name   : parity_using_assign.vhd
  4 -- Function    : Parity using direct assignment
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity parity_using_assign is
 12     port (
 13         data_in     :in  std_logic_vector (7 downto 0);
 14         parity_out  :out std_logic
 15     );
 16 end entity;
 17 
 18 architecture rtl of parity_using_assign is
 19     
 20 begin
 21 
 22     parity_out <= (data_in(0) xor data_in(1)) xor
 23                   (data_in(2) xor data_in(3)) xor
 24                   (data_in(4) xor data_in(5)) xor
 25                   (data_in(6) xor data_in(7));
 26 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : parity_using_function
  3 -- File Name   : parity_using_function.vhd
  4 -- Function    : Parity using function
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity parity_using_function is
 12     port (
 13         data_in     :in  std_logic_vector (7 downto 0);
 14         parity_out  :out std_logic
 15     );
 16 end entity;
 17 
 18 architecture rtl of parity_using_function is
 19 
 20     function parity(d_in :std_logic_vector) return std_logic is
 21         variable result :std_logic;
 22     begin
 23         result := (d_in(0) xor d_in(1)) xor
 24                   (d_in(2) xor d_in(3)) xor
 25                   (d_in(4) xor d_in(5)) xor
 26                   (d_in(6) xor d_in(7));
 27 
 28         return result;
 29 
 30     end parity;
 31 
 32 
 33 begin
 34                  -- Function Call
 35     parity_out <= parity(data_in);
 36 
 37 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : parity_using_function2
  3 -- File Name   : parity_using_function2.vhd
  4 -- Function    : Parity using function
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity parity_using_function2 is
 12     port (
 13         data_in     :in  std_logic_vector (31 downto 0);
 14         parity_out  :out std_logic
 15     );
 16 end entity;
 17 
 18 architecture rtl of parity_using_function2 is
 19 
 20     function parity (d_in :std_logic_vector) return std_logic is
 21         variable result :std_logic;
 22     begin
 23         result := '0';
 24         for i in 0 to d_in'length-1 loop
 25             result := result xor d_in(i);
 26         end loop;
 27 
 28         return result;
 29     
 30     end parity;
 31     
 32 
 33 begin
 34                  -- Function Call
 35     parity_out <= parity(data_in);
 36 
 37 end architecture;

  1 -------------------------------------------------------
  2 -- Design Name : parity_using_bitwise
  3 -- File Name   : parity_using_bitwise.vhd
  4 -- Function    : Parity using bitwise xor
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10 
 11 entity parity_using_bitwise is
 12     port (
 13         data_in     :in  std_logic_vector (7 downto 0);
 14         parity_out  :out std_logic
 15     );
 16 end entity;
 17 
 18 architecture rtl of parity_using_bitwise is
 19     
 20 begin
 21 
 22     process (data_in)
 23         variable pbit :std_logic;
 24     begin
 25         pbit := '0';
 26         for i in 0 to 7 loop
 27             pbit := pbit xor data_in(i);
 28         end loop;
 29         
 30         parity_out <= pbit;
 31 
 32     end process;
 33     
 34 end architecture;

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