1 -------------------------------------------------------
  2 -- Design Name : ram_sp_ar_aw
  3 -- File Name   : ram_sp_ar_aw.vhd
  4 -- Function    : Asynchronous read write RAM 
  5 -- Coder       : Deepak Kumar Tala (Verilog)
  6 -- Translator  : Alexander H Pham (VHDL)
  7 -------------------------------------------------------
  8 library ieee;
  9     use ieee.std_logic_1164.all;
 10     use ieee.std_logic_unsigned.all;
 11 
 12 entity ram_sp_ar_aw is
 13     generic (
 14         DATA_WIDTH :integer := 8;
 15         ADDR_WIDTH :integer := 8
 16     );
 17     port (
 18         address :in    std_logic_vector (ADDR_WIDTH-1 downto 0); -- address Input
 19         data    :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data bi-directional
 20         cs      :in    std_logic;                                -- Chip Select
 21         we      :in    std_logic;                                -- Write Enable/Read Enable
 22         oe      :in    std_logic                                 -- Output Enable
 23     );
 24 end entity;
 25 architecture rtl of ram_sp_ar_aw is
 26    ----------------Internal variables----------------
 27     constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
 28 
 29     signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);
 30 
 31     type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
 32     signal mem : RAM (0 to RAM_DEPTH-1);
 33 begin
 34 
 35    ----------------Code Starts Here------------------
 36    -- Tri-State Buffer control
 37     data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');
 38 
 39    -- Memory Write Block
 40     MEM_WRITE:
 41     process (address, data, cs, we) begin
 42        if (cs = '1' and we = '1') then
 43            mem(conv_integer(address)) <= data;
 44        end if;
 45     end process;
 46 
 47    -- Memory Read Block
 48     MEM_READ:
 49     process (address, cs, we, oe, mem) begin
 50         if (cs = '1' and we = '0' and oe = '1')  then
 51              data_out <= mem(conv_integer(address));
 52         end if;
 53     end process;
 54 
 55 end architecture;

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